Method for patterning sublithographic features

• US 8,728,945 B2
• Filed: 11/03/2011
• Issued: 05/20/2014
• Est. Priority Date: 11/03/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lytle, Steven Alan
• Primary Examiner(s): OLSEN, ALLAN W
• Application Number:
  US13/288,756
• Publication Number:
  US 20120108068A1
• Time in Patent Office: 929 Days
• Field of Search: None
• US Class Current: 438/696
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00

Abstract

A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.

Claims

1. A process of forming an integrated circuit, comprising the steps:

forming a photoresist pattern over an underlying layer with a minimum size space or hole, wherein said underlying layer comprises gate material which has been previously etched in a gate length reduction etch to form transistor gates, such that gate tips of two of said transistor gates are connected after said gate length reduction etch is completed, and wherein said photoresist pattern exposes a hole over remaining gate material between said two transistor gates;

depositing a thin film onto said photoresist pattern using an atomic layer deposition (ALD) process;

etching said thin film to form sidewalls on said photoresist pattern completely around a perimeter of said minimum size space or hole; and

etching said underlying layer while said photoresist pattern is in place, forming a sublithographic space, so that said step of etching said underlying layer separates said two transistor gates.

2. The process of claim 1 further comprising;

forming said photoresist pattern with a non minimum size hole; and

etching said underlying layer forming a non minimum size hole where a lateral dimension and a longitudinal dimension of said non minimum size hole are reduced by approximately the same amount.

3. The process of claim 1 where said thin film is silicon dioxide with a thickness in the range of 5 nm to 40 nm deposited at about 75 C.

4. The process of claim 1 where said thin film is silicon dioxide with a thickness of approximately 20 nm.

5. The process of claim 1 where a deposition temperature of said ALD process is less than 140 C.

6. A process of forming an integrated circuit, comprising the steps:

forming a hole photoresist pattern on an underlying layer with a minimum size hole, wherein said underlying layer comprises gate material which has been previously etched in a gate length reduction etch to form transistor gates, such that gate tips of two of said transistor gates are connected after said gate length reduction etch is completed, and wherein said hole photoresist pattern exposes a hole over remaining gate material between said two transistor gates;

depositing a thin film onto said hole photoresist pattern using an atomic layer deposition (ALD) process, wherein said thin film is silicon dioxide;

etching said thin film to form sidewalls on said hole photoresist pattern completely around a perimeter of said minimum size hole; and

etching said underlying layer while said hole photoresist pattern is in place to form a sublithographic hole, wherein said step of etching said underlying layer separates said two transistor gates, and said sublithographic hole is 10 nm to 80 nm below a minimum photolithographic gate tip-to-gate tip space.

7. The process of claim 6 further comprising:

forming a hole photoresist pattern with a non minimum size hole; and

etching said underlying layer to form a non sublithographic hole where a lateral and a longitudinal dimension of said non sublithographic hole are reduced by approximately an equal amount.

8. The process of claim 6 where said sublithographic hole is approximately 40 nm below said minimum photolithographic gate tip-to-gate tip space.