Semiconductor memory device

• US 8,729,545 B2
• Filed: 04/24/2012
• Issued: 05/20/2014
• Est. Priority Date: 04/28/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takahashi, Yasuyuki
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US13/454,437
• Publication Number:
  US 20120273858A1
• Time in Patent Office: 756 Days
• Field of Search: 257 68- 70, 257296-308, 257905-907, 257/43
• US Class Current: 257/43
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object is to provide a semiconductor memory device that enables low power consumption of a memory cell of a CAM including a nonvolatile memory device. Another object is to provide a semiconductor memory device without degradation due to repeated data writing. Still another object is to provide a nonvolatile memory device that enables high density of memory cells. A semiconductor memory device is provided which includes a memory circuit including a first transistor including an oxide semiconductor in a semiconductor layer, and a capacitor in which a potential corresponding to written data can be retained by turning off the first transistor; and a reference circuit for referring the written potential. The semiconductor memory device enables a high-speed search function by obtaining the address of data generated by detecting the conducting state of a second transistor in the reference circuit.

Claims

1. A semiconductor device comprising:

a first memory cell comprising;

a first transistor;

a second transistor; and

a first capacitor comprising one electrode electrically connected to one of a source and a drain of the first transistor and a gate of the second transistor;

a second memory cell comprising;

a third transistor;

a fourth transistor; and

a second capacitor comprising an electrode electrically connected to one of a source and a drain of the third transistor and a gate of the fourth transistor; and

a circuit,

wherein;

the first transistor comprises a semiconductor layer containing an oxide semiconductor;

the third transistor comprises a semiconductor layer containing an oxide semiconductor;

a gate of the first transistor and a gate of the third transistor are electrically connected to a first line;

the other electrode of the first capacitor is electrically connected to a second line;

the other electrode of the second capacitor is electrically connected to a third line;

one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor; and

the other of the source and the drain of the fourth transistor is electrically connected to the circuit.

2. The semiconductor device according to claim 1, wherein the second transistor comprises a semiconductor layer containing single crystal silicon.

3. The semiconductor device according to claim 2, wherein the first transistor is over the second transistor.

4. The semiconductor device according to claim 1, wherein the second transistor includes an oxide semiconductor layer.

5. The semiconductor device according to claim 4, wherein:

the oxide semiconductor layer of the first transistor is formed on an insulating surface; and

the oxide semiconductor layer of the second transistor is formed on the insulating surface.

6. The semiconductor device according to claim 1, wherein the circuit is a determination circuit being configured to detect a change in potential caused in accordance with conducting states or nonconducting states of the second transistor and the fourth transistor.

7. The semiconductor device according to claim 1, wherein concentration of hydrogen in the oxide semiconductor is 5×

10¹⁹ atoms/cm³ or lower.

8. A semiconductor device comprising:

a first memory cell comprising;

a first transistor;

a second transistor; and

a first capacitor comprising one electrode electrically connected to one of a source and a drain of the first transistor and a gate of the second transistor;

a second memory cell comprising;

a third transistor;

a fourth transistor; and

a second capacitor comprising an electrode electrically connected to one of a source and a drain of the third transistor and a gate of the fourth transistor; and

a circuit,

wherein;

the first transistor comprises a semiconductor layer containing an oxide semiconductor;

the second transistor comprises a semiconductor layer containing silicon;

the third transistor comprises a semiconductor layer containing an oxide semiconductor;

the fourth transistor comprises a semiconductor layer containing silicon;

a gate of the first transistor and a gate of the third transistor are electrically connected to a first line;

the other electrode of the first capacitor is electrically connected to a second line;

the other electrode of the second capacitor is electrically connected to a third line;

one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor; and

the other of the source and the drain of the fourth transistor is electrically connected to the circuit.

9. The semiconductor device according to claim 8, wherein the first transistor is over the second transistor.

10. The semiconductor device according to claim 8, wherein the circuit is a determination circuit being configured to detect a change in potential caused in accordance with conducting states or nonconducting states of the second transistor and the fourth transistor.

11. The semiconductor device according to claim 8, wherein concentration of hydrogen in the oxide semiconductor is 5×

10¹⁹ atoms/cm³ or lower.

12. A semiconductor device comprising:

a first memory cell comprising;

a first transistor;

a second transistor; and

a first capacitor comprising one electrode electrically connected to one of a source and a drain of the first transistor and a gate of the second transistor;

a second memory cell comprising;

a third transistor;

a fourth transistor; and

a second capacitor comprising an electrode electrically connected to one of a source and a drain of the third transistor and a gate of the fourth transistor; and

a circuit,

wherein;

the first transistor comprises a semiconductor layer containing an oxide semiconductor;

the third transistor comprises a semiconductor layer containing an oxide semiconductor;

a gate of the first transistor and a gate of the third transistor are electrically connected to a first line;

the other of the source and the drain of the first transistor is electrically connected to a second line;

the other of the source and the drain of the third transistor is electrically connected to a third line;

the other electrode of the first capacitor is electrically connected to a fourth line;

the other electrode of the second capacitor is electrically connected to a fifth line;

one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor; and

the other of the source and the drain of the fourth transistor is electrically connected to the circuit.

13. The semiconductor device according to claim 12, wherein the second transistor comprises a semiconductor layer containing single crystal silicon.

14. The semiconductor device according to claim 13, wherein the first transistor is over the second transistor.

15. The semiconductor device according to claim 12, wherein the second transistor includes an oxide semiconductor layer.

16. The semiconductor device according to claim 15, wherein:

the oxide semiconductor layer of the first transistor is formed on an insulating surface; and

the oxide semiconductor layer of the second transistor is formed on the insulating surface.

17. The semiconductor device according to claim 12, wherein the circuit is a determination circuit being configured to detect a change in potential caused in accordance with conducting states or nonconducting states of the second transistor and the fourth transistor.

18. The semiconductor device according to claim 12, wherein concentration of hydrogen in the oxide semiconductor is 5×

10¹⁹ atoms/cm³ or lower.