Method for manufacturing semiconductor device

• US 8,729,547 B2
• Filed: 12/26/2012
• Issued: 05/20/2014
• Est. Priority Date: 08/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Miyairi, Hidekazu, Akimoto, Kengo, Nakamura, Yasuo
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US13/727,056
• Publication Number:
  US 20130140557A1
• Time in Patent Office: 510 Days
• Field of Search: 257/E21.046, 257/E21.062, 257/E21.424, 257/E21.457, 438/621
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 21/467 using masks
• CPC Class Codes: H01L 21/4763 Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers manufacture of electrodes H01L21/28, H01L21/44
• CPC Class Codes: H01L 21/47635 After-treatment of these layers
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 : with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78633 : with a light shield
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 : the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer comprising indium, zinc, gallium and oxygen, the oxide semiconductor layer including a channel formation region;

a gate electrode adjacent to the channel formation region with a gate insulating layer therebetween;

a first n-type conductivity region comprising indium, zinc, gallium and oxygen;

a second n-type conductivity region comprising indium, zinc, gallium and oxygen;

a source electrode comprising a first metal layer over the first n-type conductivity region, wherein the source electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the first n-type conductivity region;

a drain electrode comprising a second metal layer over the second n-type conductivity region, wherein the drain electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the second n-type conductivity region,

wherein an inner side edge of the first metal layer is substantially aligned with an inner side edge of the first n-type conductivity region,

wherein an inner side edge of the second metal layer is substantially aligned with an inner side edge of the second n-type conductivity region, and

wherein the oxide semiconductor layer comprises excessive oxygen.

2. The semiconductor device according to claim 1,

wherein the first n-type conductivity region is a layer formed over the oxide semiconductor layer, and

wherein the second n-type conductivity region is a layer formed over the oxide semiconductor layer.

3. The semiconductor device according to claim 1,

wherein a thickness of the first n-type conductivity region is 2 nm to 100 nm, and

wherein a thickness of the second n-type conductivity region is 2 nm to 100 nm.

4. The semiconductor device according to claim 1,

wherein the gate insulating layer is a stacked layer comprising a first insulating layer and a second insulating layer,

wherein the first insulating layer comprises silicon and nitrogen, and

wherein the second insulating layer comprises silicon and oxygen.

5. The semiconductor device according to claim 1,

wherein the first metal layer comprises titanium, and

wherein the second metal layer comprises titanium.

6. The semiconductor device according to claim 1, further comprising a channel protective layer over the oxide semiconductor layer.

7. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.

8. The semiconductor device according to claim 1,

wherein a carrier concentration in the first n-type conductivity region is higher than a carrier concentration in the oxide semiconductor layer, and

wherein a carrier concentration in the second n-type conductivity region is higher than the carrier concentration in the oxide semiconductor layer.

9. A semiconductor device comprising:

an oxide semiconductor layer comprising indium, zinc, gallium and oxygen, the oxide semiconductor layer including a channel formation region;

a gate electrode under the channel formation region with a gate insulating layer therebetween;

a first n-type conductivity region comprising indium, zinc, gallium and oxygen;

a second n-type conductivity region comprising indium, zinc, gallium and oxygen;

a source electrode comprising a first metal layer over the first n-type conductivity region, wherein the source electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the first n-type conductivity region;

a drain electrode comprising a second metal layer over the second n-type conductivity region, wherein the drain electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the second n-type conductivity region,

wherein an inner side edge of the first metal layer is substantially aligned with an inner side edge of the first n-type conductivity region,

wherein an inner side edge of the second metal layer is substantially aligned with an inner side edge of the second n-type conductivity region, and

wherein the oxide semiconductor layer comprises excessive oxygen.

10. The semiconductor device according to claim 9,

wherein the first n-type conductivity region is a layer formed over the oxide semiconductor layer, and

wherein the second n-type conductivity region is a layer formed over the oxide semiconductor layer.

11. The semiconductor device according to claim 9,

wherein a thickness of the first n-type conductivity region is 2 nm to 100 nm, and

wherein a thickness of the second n-type conductivity region is 2 nm to 100 nm.

12. The semiconductor device according to claim 9,

wherein the first metal layer comprises titanium, and

wherein the second metal layer comprises titanium.

13. The semiconductor device according to claim 9, further comprising a channel protective layer over the oxide semiconductor layer.

14. The semiconductor device according to claim 9,

wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.

15. The semiconductor device according to claim 9,

wherein a carrier concentration in the first n-type conductivity region is higher than a carrier concentration in the oxide semiconductor layer, and

wherein a carrier concentration in the second n-type conductivity region is higher than the carrier concentration in the oxide semiconductor layer.

16. A semiconductor device comprising:

an oxide semiconductor layer comprising indium, zinc and oxygen, the oxide semiconductor layer including a channel formation region;

a gate electrode adjacent to the channel formation region with a gate insulating layer therebetween;

a first n-type conductivity region comprising indium, zinc and oxygen;

a second n-type conductivity region comprising indium, zinc and oxygen;

a source electrode comprising a first metal layer over the first n-type conductivity region, wherein the source electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the first n-type conductivity region;

a drain electrode comprising a second metal layer over the second n-type conductivity region, wherein the drain electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the second n-type conductivity region,

wherein an inner side edge of the first metal layer is substantially aligned with an inner side edge of the first n-type conductivity region,

wherein an inner side edge of the second metal layer is substantially aligned with an inner side edge of the second n-type conductivity region, and

wherein the oxide semiconductor layer comprises excessive oxygen.

17. The semiconductor device according to claim 16,

wherein the first n-type conductivity region is a layer formed over the oxide semiconductor layer, and

wherein the second n-type conductivity region is a layer formed over the oxide semiconductor layer.

18. The semiconductor device according to claim 16,

wherein a thickness of the first n-type conductivity region is 2 nm to 100 nm, and

wherein a thickness of the second n-type conductivity region is 2 nm to 100 nm.

19. The semiconductor device according to claim 16,

wherein the gate insulating layer is a stacked layer comprising a first insulating layer and a second insulating layer,

wherein the first insulating layer comprises silicon and nitrogen, and

wherein the second insulating layer comprises silicon and oxygen.

20. The semiconductor device according to claim 16,

wherein the first metal layer comprises titanium, and

wherein the second metal layer comprises titanium.

21. The semiconductor device according to claim 16, further comprising a channel protective layer over the oxide semiconductor layer.

22. The semiconductor device according to claim 16,

wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.

23. The semiconductor device according to claim 16,

wherein a carrier concentration in the first n-type conductivity region is higher than a carrier concentration in the oxide semiconductor layer, and

wherein a carrier concentration in the second n-type conductivity region is higher than the carrier concentration in the oxide semiconductor layer.

24. A semiconductor device comprising:

an oxide semiconductor layer comprising indium, zinc, gallium and oxygen, the oxide semiconductor layer including a channel formation region;

a gate electrode adjacent to the channel formation region with a gate insulating layer therebetween;

a first n-type conductivity region comprising indium, zinc, gallium and oxygen;

a second n-type conductivity region comprising indium, zinc, gallium and oxygen;

a source electrode comprising a first metal layer over the first n-type conductivity region, wherein the source electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the first n-type conductivity region;

a drain electrode comprising a second metal layer over the second n-type conductivity region, wherein the drain electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the second n-type conductivity region,

wherein an inner side edge of the first metal layer is substantially aligned with an inner side edge of the first n-type conductivity region,

wherein an inner side edge of the second metal layer is substantially aligned with an inner side edge of the second n-type conductivity region, and

wherein the gate insulating layer comprises excessive oxygen.

25. The semiconductor device according to claim 24,

wherein the first n-type conductivity region is a layer formed over the oxide semiconductor layer, and

wherein the second n-type conductivity region is a layer formed over the oxide semiconductor layer.

26. The semiconductor device according to claim 24,

wherein a thickness of the first n-type conductivity region is 2 nm to 100 nm, and

wherein a thickness of the second n-type conductivity region is 2 nm to 100 nm.

27. The semiconductor device according to claim 24,

wherein the gate insulating layer is a stacked layer comprising a first insulating layer and a second insulating layer,

wherein the first insulating layer comprises silicon and nitrogen, and

wherein the second insulating layer comprises silicon and oxygen.

28. The semiconductor device according to claim 24,

wherein the first metal layer comprises titanium, and

wherein the second metal layer comprises titanium.

29. The semiconductor device according to claim 24, further comprising a channel protective layer over the oxide semiconductor layer.

30. The semiconductor device according to claim 24,

wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.

31. The semiconductor device according to claim 24,

wherein a carrier concentration in the first n-type conductivity region is higher than a carrier concentration in the oxide semiconductor layer, and

wherein a carrier concentration in the second n-type conductivity region is higher than the carrier concentration in the oxide semiconductor layer.

32. A semiconductor device comprising:

an oxide semiconductor layer comprising indium, zinc, gallium and oxygen, the oxide semiconductor layer including a channel formation region;

a gate electrode under the channel formation region with a gate insulating layer therebetween;

a first n-type conductivity region comprising indium, zinc, gallium and oxygen;

a second n-type conductivity region comprising indium, zinc, gallium and oxygen;

a source electrode comprising a first metal layer over the first n-type conductivity region, wherein the source electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the first n-type conductivity region;

a drain electrode comprising a second metal layer over the second n-type conductivity region, wherein the drain electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the second n-type conductivity region,

wherein an inner side edge of the first metal layer is substantially aligned with an inner side edge of the first n-type conductivity region,

wherein an inner side edge of the second metal layer is substantially aligned with an inner side edge of the second n-type conductivity region, and

wherein the gate insulating layer comprises excessive oxygen.

33. The semiconductor device according to claim 32,

wherein the first n-type conductivity region is a layer formed over the oxide semiconductor layer, and

wherein the second n-type conductivity region is a layer formed over the oxide semiconductor layer.

34. The semiconductor device according to claim 32,

wherein a thickness of the first n-type conductivity region is 2 nm to 100 nm, and

wherein a thickness of the second n-type conductivity region is 2 nm to 100 nm.

35. The semiconductor device according to claim 32,

wherein the gate insulating layer is a stacked layer comprising a first insulating layer and a second insulating layer,

wherein the first insulating layer comprises silicon and nitrogen, and

wherein the second insulating layer comprises silicon and oxygen.

36. The semiconductor device according to claim 32,

wherein the first metal layer comprises titanium, and

wherein the second metal layer comprises titanium.

37. The semiconductor device according to claim 32, further comprising a channel protective layer over the oxide semiconductor layer.

38. The semiconductor device according to claim 32,

wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.

39. The semiconductor device according to claim 32,

wherein a carrier concentration in the first n-type conductivity region is higher than a carrier concentration in the oxide semiconductor layer, and

wherein a carrier concentration in the second n-type conductivity region is higher than the carrier concentration in the oxide semiconductor layer.

40. A semiconductor device comprising:

an oxide semiconductor layer comprising indium, zinc and oxygen, the oxide semiconductor layer including a channel formation region;

a gate electrode adjacent to the channel formation region with a gate insulating layer therebetween;

a first n-type conductivity region comprising indium, zinc and oxygen;

a second n-type conductivity region comprising indium, zinc and oxygen;

a source electrode comprising a first metal layer over the first n-type conductivity region, wherein the source electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the first n-type conductivity region;

a drain electrode comprising a second metal layer over the second n-type conductivity region, wherein the drain electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the second n-type conductivity region,

wherein an inner side edge of the first metal layer is substantially aligned with an inner side edge of the first n-type conductivity region,

wherein an inner side edge of the second metal layer is substantially aligned with an inner side edge of the second n-type conductivity region, and

wherein the gate insulating layer comprises excessive oxygen.

41. The semiconductor device according to claim 40,

wherein the first n-type conductivity region is a layer formed over the oxide semiconductor layer, and

wherein the second n-type conductivity region is a layer formed over the oxide semiconductor layer.

42. The semiconductor device according to claim 40,

wherein a thickness of the first n-type conductivity region is 2 nm to 100 nm, and

wherein a thickness of the second n-type conductivity region is 2 nm to 100 nm.

43. The semiconductor device according to claim 40,

wherein the gate insulating layer is a stacked layer comprising a first insulating layer and a second insulating layer,

wherein the first insulating layer comprises silicon and nitrogen, and

wherein the second insulating layer comprises silicon and oxygen.

44. The semiconductor device according to claim 40,

wherein the first metal layer comprises titanium, and

wherein the second metal layer comprises titanium.

45. The semiconductor device according to claim 40, further comprising a channel protective layer over the oxide semiconductor layer.

46. The semiconductor device according to claim 40,

wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.

47. The semiconductor device according to claim 40,

wherein a carrier concentration in the first n-type conductivity region is higher than a carrier concentration in the oxide semiconductor layer, and

wherein a carrier concentration in the second n-type conductivity region is higher than the carrier concentration in the oxide semiconductor layer.

48. A semiconductor device comprising:

an insulating layer comprising silicon and excessive oxygen;

an oxide semiconductor layer in contact with the insulating layer, the oxide semiconductor layer including a channel forming region; and

a gate electrode adjacent to the oxide semiconductor layer.

49. The semiconductor device according to claim 48,

wherein the oxide semiconductor layer comprises indium.

50. The semiconductor device according to claim 48,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

51. The semiconductor device according to claim 48,

wherein the insulating layer is located below the oxide semiconductor layer.

52. The semiconductor device according to claim 48,

wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.

53. The semiconductor device according to claim 48,

wherein the oxide semiconductor layer comprises excessive oxygen.

54. A semiconductor device comprising:

a gate electrode;

an insulating layer over the gate electrode, the insulating layer comprising silicon and excessive oxygen; and

an oxide semiconductor layer over the gate electrode, the oxide semiconductor layer including a channel forming region and being in contact with the insulating layer.

55. The semiconductor device according to claim 54,

wherein the oxide semiconductor layer comprises indium.

56. The semiconductor device according to claim 54,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

57. The semiconductor device according to claim 54,

wherein the insulating layer is located between the gate electrode and the oxide semiconductor layer.

58. The semiconductor device according to claim 54,

wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.

59. A semiconductor device comprising:

an insulating layer comprising silicon and oxygen;

an oxide semiconductor layer in contact with the insulating layer, the oxide semiconductor layer including a channel forming region; and

a gate electrode adjacent to the oxide semiconductor layer,

wherein the oxide semiconductor layer contains excessive oxygen.

60. The semiconductor device according to claim 59,

wherein the oxide semiconductor layer comprises indium.

61. The semiconductor device according to claim 59,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

62. The semiconductor device according to claim 59,

wherein the insulating layer is located below the oxide semiconductor layer.

63. The semiconductor device according to claim 59,

wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.

64. A semiconductor device comprising:

a gate electrode;

an insulating layer over the gate electrode, the insulating layer comprising silicon and oxygen; and

an oxide semiconductor layer over the gate electrode, the oxide semiconductor layer including a channel forming region and being in contact with the insulating layer,

wherein the oxide semiconductor layer contains excessive oxygen.

65. The semiconductor device according to claim 64,

wherein the oxide semiconductor layer comprises indium.

66. The semiconductor device according to claim 64,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

67. The semiconductor device according to claim 64,

wherein the insulating layer is located between the gate electrode and the oxide semiconductor layer.

68. The semiconductor device according to claim 64,

wherein the oxide semiconductor layer is an amorphous oxide semiconductor layer.