Semiconductor switch device

• US 8,729,605 B2
• Filed: 06/11/2012
• Issued: 05/20/2014
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Takaishi, Masaru
• Primary Examiner(s): Mandala, Michelle
• Application Number:
  US13/493,103
• Publication Number:
  US 20120267710A1
• Time in Patent Office: 708 Days
• Field of Search: 257/106, 257/199, 257/249, 257/288, 257/401, 257/481, 257/551, 257/594, 257/603, 257/E29.335, 257/E21.356, 257/E21.355
• US Class Current: 257/199
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 29/866 Zener diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

Provided is a semiconductor device in which on-resistance is largely reduced. In a region (2a) of an N type epitaxial layer (2) of the semiconductor device 20, each region between neighboring trenches (3) is blocked with a depletion layer (14) formed around a trench (3) so that a current passage (12) is interrupted, while a part of the depletion layer (14) formed around the trench (3) is deleted so that the current passage (12) is opened. In a region (2b), a junction portion (8) between the N type epitaxial layer (2) and a P⁺ type diffusion region (7) makes a Zener diode (8).

Claims

1. A semiconductor device comprising:

a first region of one conductivity type;

a second region of the one conductivity type provided on the first region;

a third region of an inverse conductivity type provided on the first region so as to be contiguous with the second region and the first region; and

a switching device provided in the second region,

wherein a first diffusion region of the one conductivity type electrically connected to the second region is formed in an upper region within the third region opposite from the first region,

wherein a trench in which a gate electrode is embedded is formed in the second region, and the gate electrode is embedded so as to fill the trench halfway across a depth thereof, and

wherein an interlayer insulator film is embedded in a remaining part of the trench where the gate electrode is not embedded.

2. The semiconductor device according to claim 1, wherein

an electrode layer which makes ohmic contact with the second region is formed above the second region,

the electrode layer extends to reach, and makes ohmic contact with, the first diffusion region electrically connected to the second region, and

the second region and the first diffusion region are electrically connected to each other via the electrode layer.

3. The semiconductor device according to claim 1, wherein

the first diffusion region comprises a plurality of first diffusion regions of the one conductivity type, and the plurality of first diffusion regions and a plurality of second diffusion regions of the inverse conductivity type are formed in the third region,

the plurality of first diffusion regions and the plurality of second diffusion regions are arranged alternately one by one from a second region side outward away from the second region side, with one of the first diffusion regions located at an innermost position closest to the second region, and

the first diffusion region located at the innermost position is the first diffusion region electrically connected to the second region.

4. The semiconductor device according to claim 3, wherein

the switching device provided in the second region includes a gate electrode, and

one of the plurality of first diffusion regions located between the second diffusion regions is electrically connected to the gate electrode.

5. The semiconductor device according to claim 3, wherein

the plurality of first diffusion regions and the plurality of second diffusion regions are so arranged that one of the first diffusion regions is located at an outermost position farthest away from the second region, and

the first diffusion region located at the outermost position is electrically connected to the first region.

6. The semiconductor device according to claim 5, further comprising a fourth region provided on the first region and arranged outside the third region opposite from the second region, wherein

the first diffusion region located at the outermost position is formed so as to extend from the third region to the fourth region, and is electrically connected via the fourth region to the first region.

7. The semiconductor device according to claim 3, wherein the plurality of first diffusion regions and the plurality of second diffusion regions are formed so as to surround the second region.

8. The semiconductor device according to claim 3, wherein

the plurality of first diffusion regions and the plurality of second diffusion regions are diffusion regions formed by injecting an impurity into the third region from an upper surface side thereof, and

a thickness of the plurality of second diffusion regions from an upper surface of the third region is larger than a thickness of the plurality of first diffusion regions from the upper surface of the third region.

9. The semiconductor device according to claim 1, wherein as seen in a sectional view, a width of the third region is larger than a width of the trench.

10. The semiconductor device according to claim 1, wherein

an upper surface of the interlayer insulator film embedded in the trench is flush with an upper surface of the second region.