Nonvolatile semiconductor memory device

• US 8,729,620 B2
• Filed: 03/20/2007
• Issued: 05/20/2014
• Est. Priority Date: 03/21/2006
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Asami, Yoshinobu, Takano, Tamae, Furuno, Makoto
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Diaz, Jose R
• Application Number:
  US11/723,483
• Publication Number:
  US 20070235793A1
• Time in Patent Office: 2,618 Days
• Field of Search: 257314-316, 257/324, 257/319
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

It is an object to provide a nonvolatile semiconductor memory device having excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate, a second insulating layer, and a control gate are provided. The floating gate has at least a two-layer structure, and a first layer in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. Furthermore, by setting an energy level at the bottom of the conduction band of the floating gate lower than that of the channel forming region of the semiconductor layer, injectability of carriers and a charge-retention property can be improved.

Claims

1. A nonvolatile semiconductor memory device comprising:

a substrate;

a semiconductor layer over the substrate, the semiconductor layer including a channel forming region between a pair of impurity regions which are formed apart from each other;

a first insulating layer over the semiconductor layer;

a floating gate over the channel forming region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the floating gate includes at least a first layer which is in contact with the first insulating layer and a second layer formed over the first layer, and the first layer comprises germanium and oxygen,

wherein the semiconductor layer is an island-like semiconductor layer formed on an insulating surface,

wherein the first insulating layer covers the channel forming region and the pair of impurity regions, and

wherein the semiconductor layer comprises a low-concentration impurity region which overlaps with the control gate, does not overlap with the floating gate, and has the same conductivity type as a conductivity type of the pair of impurity regions.

2. The nonvolatile semiconductor memory device according to claim 1, wherein the first insulating layer comprises a layer in which a silicon oxide layer and a silicon nitride layer are sequentially stacked from the semiconductor layer side.

3. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

4. The nonvolatile semiconductor memory device according to claim 1, wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in the channel length direction.

5. The nonvolatile semiconductor memory device according to claim 1, wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in the channel length direction.

6. The nonvolatile semiconductor memory device according to claim 1, wherein an edge of the floating gate in a channel width direction is provided over the semiconductor layer and an impurity region having a conductivity type which is different from a conductivity type of the pair of impurity regions.

7. The nonvolatile semiconductor memory device according to claim 1, wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer, wherein the floating gate is in contact with the silicon nitride layer.

8. The nonvolatile semiconductor memory device according to claim 1, wherein the first insulating layer comprises a silicon oxide layer formed by a plasma treatment to the semiconductor layer and a silicon nitride layer formed by a plasma treatment to the silicon oxide layer.

9. The nonvolatile semiconductor memory device according to claim 1, wherein the second layer comprises metal oxide.

10. The nonvolatile semiconductor memory device according to claim 1, wherein the second layer comprises metal nitride.

11. A nonvolatile semiconductor memory device comprising:

a semiconductor layer including a channel forming region between a pair of impurity regions which are formed apart from each other;

a first insulating layer over the channel forming region;

a floating gate over the channel forming region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the floating gate includes at least a first layer which is in contact with the first insulating layer and a second layer formed over the first layer, and the first layer comprises germanium and oxygen,

wherein an edge of the first layer in a channel length direction and an edge of the second layer in the channel length direction are substantially aligned, and

wherein the semiconductor layer comprises a low-concentration impurity region which overlaps with the control gate, does not overlap with the floating gate, and has the same conductivity type as a conductivity type of the pair of impurity regions.

12. A nonvolatile semiconductor memory device according to claim 11, wherein the first insulating layer comprises a layer in which a silicon oxide layer and a silicon nitride layer are sequentially stacked from the semiconductor layer side.

13. A nonvolatile semiconductor memory device according to claim 11, wherein the semiconductor layer is an island-like semiconductor layer formed on an insulating surface.

14. The nonvolatile semiconductor memory device according to claim 11, wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

15. The nonvolatile semiconductor memory device according to claim 11, wherein an edge of the floating gate in the channel length direction extends beyond an edge of the control gate in the channel length direction.

16. The nonvolatile semiconductor memory device according to claim 11, wherein an edge of the control gate in the channel length direction extends beyond an edge of the floating gate in the channel length direction.

17. The nonvolatile semiconductor memory device according to claim 11, wherein an edge of the floating gate in a channel width direction is provided over the semiconductor layer and an impurity region having a conductivity type which is different from a conductivity type of the pair of impurity regions.

18. The nonvolatile semiconductor memory device according to claim 11, wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer, wherein the floating gate is in contact with the silicon nitride layer.

19. The nonvolatile semiconductor memory device according to claim 11, wherein the first insulating layer comprises a silicon oxide layer formed by a plasma treatment to the semiconductor layer and a silicon nitride layer formed by a plasma treatment to the silicon oxide layer.

20. The nonvolatile semiconductor memory device according to claim 11, wherein the second layer comprises metal oxide.

21. The nonvolatile semiconductor memory device according to claim 11, wherein the second layer comprises metal nitride.

22. A nonvolatile semiconductor memory device comprising:

a substrate;

a semiconductor layer over the substrate, the semiconductor layer including a channel forming region between a pair of impurity regions which are formed apart from each other;

a first insulating layer over the semiconductor layer;

a floating gate over the channel forming region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the floating gate includes at least a first layer which is in contact with the first insulating layer and a second layer formed over the first layer, and the first layer comprises germanium and oxygen and has a thickness of greater than or equal to 1 nm and less than or equal to 20 nm,

wherein the semiconductor layer is an island-like semiconductor layer formed on the substrate,

wherein the first insulating layer covers the channel forming region and the pair of impurity regions, and

wherein the semiconductor layer comprises a low-concentration impurity region which overlaps with the control gate, does not overlap with the floating gate, and has the same conductivity type as a conductivity type of the pair of impurity regions.

23. A nonvolatile semiconductor memory device according to claim 22, wherein the first insulating layer comprises a layer in which a silicon oxide layer and a silicon nitride layer are sequentially stacked from the semiconductor layer side.

24. The nonvolatile semiconductor memory device according to claim 22, wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

25. The nonvolatile semiconductor memory device according to claim 22, wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in the channel length direction.

26. The nonvolatile semiconductor memory device according to claim 22, wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in the channel length direction.

27. The nonvolatile semiconductor memory device according to claim 22, wherein an edge of the floating gate in a channel width direction is provided over the semiconductor layer and an impurity region having a conductivity type which is different from a conductivity type of the pair of impurity regions.

28. The nonvolatile semiconductor memory device according to claim 22, wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer, wherein the floating gate is in contact with the silicon nitride layer.

29. The nonvolatile semiconductor memory device according to claim 22, wherein the first insulating layer comprises a silicon oxide layer formed by a plasma treatment to the semiconductor layer and a silicon nitride layer formed by a plasma treatment to the silicon oxide layer.

30. The nonvolatile semiconductor memory device according to claim 22, wherein the second layer comprises metal oxide.

31. The nonvolatile semiconductor memory device according to claim 22, wherein the second layer comprises metal nitride.