Strained channel integrated circuit devices

• US 8,729,627 B2
• Filed: 05/14/2010
• Issued: 05/20/2014
• Est. Priority Date: 05/14/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yen-Chun, Lin, Da-Wen, Cheng, Ming-Lung
• Primary Examiner(s): Jahan, Bilkis
• Application Number:
  US12/780,124
• Publication Number:
  US 20110278676A1
• Time in Patent Office: 1,467 Days
• Field of Search: 257/337, 257/343, 257/344, 257/347, 257/350, 257/394, 257/376, 257329-333, 257/377, 257382-385, 257/503, 257335-336, 257/408
• US Class Current: 257/330
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers. The second gate structure includes a high-k dielectric layer adjacent the second channel region, and a metal layer.

Claims

1. A device comprising:

a substrate having a first strained channel region and a second strained channel region therein, the second channel region being strained in a different manner than the first channel region;

a first gate structure including;

a dielectric layer disposed at least partly over the first channel region, the dielectric layer including an interfacial layer physically in contact with the first channel region;

a barrier layer disposed at least partly over the first channel region and physically in contact with the dielectric layer;

a first conductive layer disposed over the barrier layer, and having a characteristic with a first value;

a strain-inducing conductive layer disposed over the first conductive layer, and having the characteristic with a second value, wherein the second value is different from the first value; and

a second conductive layer disposed over the strain-inducing conductive layer, and having the characteristic with the first value; and

a second gate structure including;

a high-k dielectric layer disposed at least partly over the second channel region;

a U-shaped work function metal layer disposed over the high-k dielectric layer, the U-shaped work function metal layer forming an opening having opposing surfaces therein; and

a metal fill layer disposed at least partially within the opening such that the metal fill layer is in physical contact with the opposing surfaces.

2. The device according to claim 1, wherein the characteristic is one of a thermal expansion coefficient and a crystal lattice constant.

3. The device according to claim 2,

wherein the characteristic is the crystal lattice constant;

and

wherein the first and second conductive layers both have a first thermal expansion coefficient and the strain-inducing conductive layer has a second thermal expansion coefficient different from the first thermal expansion coefficient.

4. The device according to claim 3, wherein the first and second conductive layers are doped polysilicon and the strain-inducing conductive layer is silicon germanium (SiGe).

5. The device according to claim 1,

wherein the substrate includes first and second upwardly-extending projections, the first channel region being at least partly in the first projection and the second channel region being at least partly in the second projection;

wherein the first gate structure engages the first projection adjacent to the first channel region; and

wherein the second gate structure engages the second projection adjacent to the second channel region.

6. The device according to claim 5, wherein the first and second conductive layers are doped polysilicon and the strain-inducing conductive layer is silicon germanium (SiGe).

7. The device according to claim 6, wherein the strain-inducing conductive layer has a thickness in a range of approximately 300 to 450 angstroms and the first and second conductive layers each have a thickness in a range of approximately 50 to 200 angstroms.

8. The device according to claim 1, wherein the strain in the first channel region is tensile strain and the strain in the second channel region is compression strain.

9. A device comprising:

a substrate;

first and second projections extending upwardly from the substrate, the first projection having a tensile-strained first channel region therein and the second projection having a compression-strained second channel region therein; and

first and second gate structures engaging the first and second projections adjacent to the first and second channel regions, respectively;

wherein the first gate structure includes;

a dielectric layer adjacent the first channel region;

a first conductive layer disposed over the dielectric layer;

a strain-inducing conductive layer disposed over the first conductive layer; and

a second conductive layer disposed over the strain-inducing conductive layer; and

wherein the second gate structure includes;

a high-k dielectric layer adjacent the second channel region; and

a metal layer disposed over the high-k dielectric layer.

10. The device according to claim 9,

wherein the first and second conductive layers are doped polysilicon and each have a first thermal expansion coefficient and a first crystal lattice constant;

and

wherein the strain-inducing conductive layer has a second thermal expansion coefficient different from the first thermal expansion coefficient, and a second crystal lattice constant different from the first crystal lattice constant.

11. The device according to claim 10, wherein the strain-inducing conductive layer is silicon germanium (SiGe).

12. The device according to claim 11, wherein the strain-inducing conductive layer has a thickness in a range of approximately 300 to 450 angstroms and the first and second conductive layers each have a thickness in a range of approximately 50 to 200 angstroms.

13. The device according to claim 9, including:

first epitaxial growths on portions of the first projection at each side of the first gate structure, the first epitaxial growths imparting tensile strain to the first channel region; and

second epitaxial growths on portions of the second projection at each side of the second gate structure, the second epitaxial growths imparting compressive strain to the second channel region.

14. The device according to claim 13, wherein the first epitaxial growths are epitaxial silicon and the second epitaxial growths are epitaxial silicon germanium (SiGe).

15. The device according to claim 9, wherein the second gate structure includes a work function layer disposed between the high-k dielectric layer and the metal layer.

16. A device comprising:

a substrate;

a first fin-like field effect transistor (FinFET) disposed on the substrate, the first FinFET including;

a first strained channel region;

a first dielectric layer disposed at least partly over the first strained channel region, the first dielectric layer including an interfacial layer physically in contact with the first strained channel region;

a barrier layer disposed at least partly over the first strained channel region and physically in contact with the first dielectric layer;

a first polysilicon layer disposed at least partly over the first strained channel region and physically in contact with the barrier layer;

a strain-inducing layer disposed at least above the first strained channel region and imparting at least a portion of the strain in the first strained channel region; and

a second polysilicon layer disposed at least partly over the first strained channel region and physically in contact with the strain-inducing layer; and

a second FinFET disposed on the substrate, the second FinFET including;

a second strained channel region, the second strained channel region being strained in a different manner than the first strained channel region;

a high-k second dielectric layer disposed at least above the second strained channel region;

a U-shaped work function metal layer disposed over the high-k second dielectric layer, the U-shaped work function metal layer forming an opening having opposing surfaces therein; and

a metal fill layer disposed at least partially within the opening such that the metal fill layer is in physical contact with the opposing surfaces.

17. The device according to claim 16, wherein the first FinFET further includes first epitaxial growths disposed on either side of the first strained channel region, the first epitaxial growths imparting a further portion of the strain in the first strained channel region.

18. The device according to claim 17, wherein the second FinFET includes second epitaxial growths disposed on either side of the second strained channel region, the second epitaxial growths being of a different material than the first epitaxial growths and imparting the strain in the second strained channel region.

19. The device according to claim 16, wherein the strain in the first strained channel region is tensile strain and the strain in the second strained channel region is compression strain.