FinFET with high mobility and strain channel

• US 8,729,634 B2
• Filed: 06/15/2012
• Issued: 05/20/2014
• Est. Priority Date: 06/15/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Kuo-Ching, Li, Hou-Ju, Liang, Chun-Sheng, Lai, Kao-Ting, Ting, Kuo-Chiang, Wu, Chi-Hsi, Shen, Chun-Liang
• Primary Examiner(s): Such, Matthew W.
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US13/525,050
• Publication Number:
  US 20130334606A1
• Time in Patent Office: 704 Days
• Field of Search: 257/308, 257/722, 257/E21.014, 257/288, 257/368, 438/294
• US Class Current: 257/368
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

An integrated circuit device includes a fin at least partially embedded in a shallow trench isolation (STI) region and extending between a source and a drain. The fin is formed from a first semiconductor material and having a trimmed portion between first and second end portions. A cap layer, which is formed from a second semiconductor material, is disposed over the trimmed portion of the fin to form a high mobility channel. A gate electrode structure is formed over the high mobility channel and between the first and second end portions.

Claims

1. An integrated circuit device, comprising:

a fin extending between a source and a drain, the fin having a trimmed portion between first and second end portions, the trimmed portion having a reduced profile relative to the first and second end portions and covered by a cap layer, the trimmed portion and the first and second end portions formed from a first semiconductor material, the cap layer formed from a second semiconductor material different than the first semiconductor material to form a high mobility channel; and

a gate electrode structure formed over the high mobility channel between the first and second end portions.

2. The integrated circuit device of claim 1, wherein the first semiconductor material is silicon and the second semiconductor material is silicon germanium.

3. The integrated circuit device of claim 1, wherein the second semiconductor material is one of silicon germanium, germanium, and an III-V semiconductor alloy.

4. The integrated circuit device of claim 1, wherein the high mobility channel includes a second cap layer disposed over the cap layer, the second cap layer formed from the first semiconductor material.

5. The integrated circuit device of claim 1, wherein the high mobility channel is configured to generate one of tension and compression in the fin.

6. The integrated circuit device of claim 1, wherein a thickness of the high mobility channel is less than a thickness of at least one of the first end portion and the second end portion of the fin.

7. The integrated circuit device of claim 1, wherein the trimmed portion of the fin has one of a square, rectangle, trapezium, triangle, hexagon, octagon, inverted-trapezium, arc, and plane fin trim profile.

8. The integrated circuit device of claim 1, wherein the high mobility channel has one of a square, rectangle, trapezium, triangle, partial hexagon, hexagon, octagon, inverted-trapezium, and arc channel profile.

9. The integrated circuit device of claim 1, wherein the fin is at least partially embedded in a shallow trench isolation (STI) region.

10. An integrated circuit device, comprising:

a fin extending between a source and a drain, the fin having a trimmed portion between first and second end portions, the trimmed portion having a reduced profile relative to the first and second end portions and covered by first and second cap layers, the trimmed portion, the first and second end portions, and the second cap layer formed from a first semiconductor material, the first cap layer formed from a second semiconductor material different than the first semiconductor material to form a high mobility channel; and

a gate electrode structure formed over the high mobility channel inward of the first and second end portions.

11. The integrated circuit device of claim 10, wherein the first semiconductor material is silicon and the second semiconductor material is one of silicon germanium, germanium, and an III-V semiconductor alloy.

12. The integrated circuit device of claim 10, wherein the high mobility channel is configured to generate one of tension and compression in the fin.

13. The integrated circuit device of claim 10, wherein a thickness of the high mobility channel is less than a thickness of at least one of the first end portion and the second end portion of the fin.

14. The integrated circuit device of claim 10, wherein the trimmed portion of the fin has one of a square, rectangle, trapezium, triangle, hexagon, octagon, inverted-trapezium, arc, and plane fin trim profile.

15. The integrated circuit device of claim 10, wherein the high mobility channel has one of a square, rectangle, trapezium, triangle, partial hexagon, hexagon, octagon, inverted-trapezium, and arc channel profile.

16. The integrated circuit device of claim 10, wherein a first spacer is disposed adjacent to the source and over the first end portion of the fin, and a second spacer is disposed adjacent to the drain and over the second end portion of the fin.

17. The integrated circuit device of claim 10, wherein the fin is at least partially embedded in a shallow trench isolation (STI) region.

18. A method of forming a fin field effect transistor (FinFET) device, comprising:

forming a fin from a first semiconductor material, the fin disposed between a source and a drain and at least partially embedded in a shallow trench isolation (STI) region;

trimming a portion of the fin between first and second end portions to form a trimmed portion such that the portion trimmed has a reduced profile relative to the first and second end portions;

capping the trimmed portion with a second semiconductor material to form a high mobility channel; and

forming a gate electrode structure over the high mobility channel and between the first and second end portions.

19. The method of claim 18, further comprising capping the second semiconductor material with the first semiconductor material to form the high mobility channel.

20. The method of claim 18, further comprising generating at least one of tension and compression in the fin with the high mobility channel.