Assembly having stacked die mounted on substrate

• US 8,729,690 B2
• Filed: 12/27/2012
• Issued: 05/20/2014
• Est. Priority Date: 04/13/2004
• Status: Active Grant

• Current Assignee: Invensas Corporation, Vertical Circuits Solutions, Inc.
• Original Assignee: Invensas Corporation
• Inventors: Vindasius, Al, Robinson, Marc E., Jacobsen, Larry, Almen, Donald
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US13/728,246
• Publication Number:
  US 20130207249A1
• Time in Patent Office: 509 Days
• Field of Search: 257/686, 257/777, 257/E23.085
• US Class Current: 257/686
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 25/00 Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Metal rerouting interconnects at one or more sides of a die or multiple die segments can form edge bonding pads for electrical connection. Insulation can be applied to surfaces of the die or multiple die segments after optional thinning and singulation, and openings can be made in the insulation to the electrical connection pads. After being placed atop one another in a stack, vertically adjacent die or die segments can be electrically interconnected using a flexible bond wire or bond ribbon attached to an electrical connection pad exposed within such opening, the bond wire or ribbon protruding horizontally, and an electrically conductive polymer, or epoxy, filaments or lines can be applied to the stack.

Claims

1. A semiconductor die assembly, comprising:

a die stack comprising a first die mounted on a substrate and at least one additional die stacked over said first die mounted on said substrate, said first die and each said additional die having a plurality of peripheral electrical connection sites arrayed in a row near and generally parallel to a peripheral edge of said die, at least one die selected from said first die and said at least one additional die being a memory die, and dielectric spacers maintaining a fixed spacing between the at least one additional die and the first die, and a conducting element electrically connected to at least one of said peripheral electrical connection sites on at least one of said die and extending from said at least one peripheral electrical connection site toward said peripheral die edge on said at least one of said die; and

the substrate having an electrical connection land at a die mount side thereof, wherein

said at least one of said peripheral electrical connection sites is electrically connected to said electrical connection land on said substrate by an electrically conductive polymer element applied to a side of said die stack adjacent said peripheral die edge, said electrically conductive polymer element contacting said conducting element and being electrically connected to said land.

2. The assembly of claim 1, wherein adjacent die of the first die and the at least one additional die are attached to one another with an electrically insulating material.

3. The assembly of claim 2, wherein the spacers are disposed in the electrically insulating material between the adjacent die.

4. The assembly of claim 2, wherein the spacers include spheres.

5. The assembly of claim 4, wherein the spheres include spheres made of glass, ceramic or quartz.

6. A semiconductor die assembly, comprising:

a die stack comprising a first die mounted on a substrate and at least one additional die stacked over said first die mounted on said substrate, said first die and each said additional die having a plurality of peripheral electrical connection sites arrayed in a row near and generally parallel to a peripheral edge of said die, and a conducting element electrically connected to at least one of said peripheral electrical connection sites on at least one of said die and extending from said at least one peripheral electrical connection site toward said peripheral die edge on said at least one of said die;

the substrate having an electrical connection land at a die mount side thereof, wherein

said at least one of said peripheral electrical connection sites is electrically connected to said electrical connection land on said substrate by an electrically conductive polymer element applied to a side of said die stack adjacent said peripheral die edge, said electrically conductive polymer element contacting said conducting element and being electrically connected to said land; and

a heatsink covering the die stack.

7. The assembly of claim 6 wherein said conducting element extends into the electrically conductive polymer element.

8. The assembly of claim 6, said additional die and said first die mounted on said substrate comprising a plurality of die;

wherein said at least one interconnection site on at least a first one of said plurality of die is electrically connected to said at least one interconnection site on at least a second one of said plurality of die by an electrically conductive polymer element applied to a side of said die stack adjacent said peripheral edge,

said electrically conductive polymer element contacting a said conducting element electrically connected to said at least one interconnection site on each of said plurality of die.

9. The assembly of claim 6 wherein said peripheral interconnection site on any one of more of said die comprises an original peripheral die pad.

10. The assembly of claim 6 wherein any one of more of said die is rerouted to connect original die pads to peripheral interconnection sites.

11. The assembly of claim 6, further comprising an electrical insulator between any one of more of said die and the electrically conductive polymer element.

12. The assembly of claim 6 wherein the electrical insulator comprises a conformal coating.

13. The assembly of claim 12 wherein the conformal coating has openings above selected ones of the interconnection sites.

14. The assembly of claim 6 wherein the electrically conductive polymer element is oriented generally perpendicular to the die mount side of the substrate.

15. The assembly of claim 6 wherein said conducting element comprises a lead frame lead.

16. The assembly of claim 6, further comprising an underfill between said first die and said substrate.

17. The assembly of claim 6, wherein said substrate comprises a multi-layer substrate.

18. The assembly of claim 17 wherein said multi-layer substrate comprises a heat sinking layer.

19. The assembly of claim 18 wherein said heat sinking layer is a metal layer.