Wafer level package and a method of forming a wafer level package

• US 8,729,695 B2
• Filed: 09/25/2009
• Issued: 05/20/2014
• Est. Priority Date: 09/25/2009
• Status: Expired due to Fees

• Current Assignee: Agency For Science Technology and Research (Government of Singapore), Seiko Instruments Incorporated (Seiko Group)
• Original Assignee: Agency For Science Technology and Research (Government of Singapore), Seiko Instruments Incorporated (Seiko Group)
• Inventors: Premachandran, Chirayarikathu Veedu Sankarapillai, Kumar, Rakesh, Ranganathan, Nagarajan, Choi, Won Kyoung, Liao, Ebin, Mitsuoka, Yasuyuki, Takahashi, Hiroshi, Mitsusue, Ryuta
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US13/497,611
• Publication Number:
  US 20130020713A1
• Time in Patent Office: 1,698 Days
• Field of Search: 257/678, 257/684, 257/688, 257/704, 257/710, 257/773, 257/E23.18, 257/E23.193, 438/53, 438/106, 438/127
• US Class Current: 257/704
• CPC Class Codes: B81B 2207/092 Buried interconnects in the substrate or in the lid
• CPC Class Codes: B81B 2207/093 Conductive package seal
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/16315 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided.

Claims

1. A wafer level package comprising:

a device wafer including a MEMS device;

a cap wafer disposed over the device wafer;

at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer; and

a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device;

wherein the conformal sealing ring is configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer is bonded to the cap wafer;

wherein the wafer level package further comprises a first electrical interconnect disposed on a first cap surface of the cap wafer and in electrical contact with the at least one first interconnect;

wherein the first electrical interconnect is configured to route the at least one first interconnect along the first cap surface of the cap wafer to crossing the conformal sealing ring to the outside of the sealed environment;

wherein the wafer level package further comprises a cap dielectric layer disposed on the first cap surface of the cap wafer, a ground contact disposed on the cap dielectric layer, and a first electrical interconnect dielectric layer disposed over the ground contact;

wherein the conformal sealing ring is connected to the ground contact via an opening in the first electrical interconnect dielectric layer.

2. The wafer level package of claim 1, further comprising at least one second interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer.

3. The wafer level package of claim 2, wherein the at least one second interconnect is disposed within the conformal sealing ring.

4. The wafer level package of claim 2, wherein the at least one first interconnect is disposed on one side of the MEMS device and the at least one second interconnect is disposed on another side of the MEMS device.

5. The wafer level package of claim 2, further comprising a second electrical interconnect disposed on the cap wafer and in electrical contact with the at least one second interconnect.

6. The wafer level package of claim 5, wherein the second electrical interconnect is configured to route the at least one second interconnect along the first cap surface of the cap wafer to crossing the conformal sealing ring to the outside of the sealed environment.

7. The wafer level package of claim 2 wherein the at least one first interconnect is electrically isolated from the conformal sealing ring and the at least one second interconnect is electrically isolated from the conformal sealing ring.

8. The wafer level package of claim 1, further comprising at least one third interconnect disposed between the device wafer and the cap wafer.

9. The wafer level package of claim 8, wherein the at least one third interconnect is disposed outside of the conformal sealing ring.

10. The wafer level package of claim 1, wherein the conformal sealing ring is connected to a ground connection.

11. A method of forming a wafer level package comprising:

forming a device wafer including a MEMS device;

forming a cap wafer over the device wafer;

forming at least one first interconnect between the device wafer and the cap wafer such that the at least one first interconnect is configured to provide an electrical connection between the device wafer and the cap wafer; and

forming a conformal sealing ring between the device wafer and the cap wafer such that the conformal sealing ring is configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device;

wherein forming the conformal sealing ring comprises forming the conformal sealing ring such that the conformal sealing ring is configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer is bonded to the cap wafer;

wherein the method further comprises forming a first electrical interconnect on a first cap surface of the cap wafer and in electrical contact with the at least one first interconnect;

wherein forming the first electrical interconnect comprises forming the first electrical interconnect such that the first electrical interconnect is configured to route the at least one first interconnect along the first cap surface of the cap wafer to crossing the conformal sealing ring to the outside of the sealed environment;

wherein the method further comprises forming a cap dielectric layer on the first cap surface of the cap wafer, forming a ground contact disposed on the cap dielectric layer, and forming a first electrical interconnect dielectric layer disposed over the ground contact;

wherein the method further comprises connecting the conformal sealing ring to the ground contact via an opening in the first electrical interconnect dielectric layer.

12. The method of claim 11, further comprising forming at least one second interconnect between the device wafer and the cap wafer such that the at least one second interconnect is configured to provide an electrical connection between the device wafer and the cap wafer.

13. The method of claim 12, wherein forming the at least one second interconnect comprises forming the at least one second interconnect within the conformal sealing ring.

14. The method of claim 12, wherein forming the at least one first interconnect and forming the at least one second interconnect comprises forming the at least one first interconnect on one side of the MEMS device and forming the at least one second interconnect on another side of the MEMS device.

15. The method of claim 12, further comprising forming a second electrical interconnect on the cap wafer and in electrical contact with the at least one second interconnect.

16. The method of claim 15, wherein forming the second electrical interconnect comprises forming the second electrical interconnect such that the second electrical interconnect is configured to route the at least one second interconnect along the first cap surface of the cap wafer to crossing the conformal sealing ring to the outside of the sealed environment.

17. The method of claim 12, wherein forming the at least one first interconnect and the at least one second interconnect comprises forming the at least one first interconnect and the at least one second interconnect such that the at least one first interconnect is electrically isolated from the conformal sealing ring and the at least one second interconnect is electrically isolated from the conformal sealing ring.

18. The method of claim 11, further comprising forming at least one third interconnect between the device wafer and the cap wafer.

19. The method of claim 18, wherein forming the at least one third interconnect comprises forming the at least one third interconnect outside of the conformal sealing ring.

20. The method of claim 11, wherein forming the conformal sealing ring comprises forming the conformal sealing ring such that the conformal sealing ring is connected to a ground connection.