Schemes for forming barrier layers for copper in interconnect structures

• US 8,729,703 B2
• Filed: 05/09/2013
• Issued: 05/20/2014
• Est. Priority Date: 11/21/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chen, Hai-Ching, Bao, Tien-I
• Primary Examiner(s): Sarkar, Asok K
• Application Number:
  US13/890,981
• Publication Number:
  US 20130249097A1
• Time in Patent Office: 376 Days
• Field of Search: None
• US Class Current: 257/751
• CPC Class Codes: H01L 21/322 to modify their internal properties, e.g. to produce internal imperfections
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Claims

1. A semiconductor structure comprising:

a dielectric layer over a substrate;

an opening extending from a top surface of the dielectric layer into the dielectric layer;

a first barrier layer lining the opening;

a conductive wiring in a remaining portion of the opening, wherein a top edge of the first barrier layer is recessed from at least a portion of a sidewall of the conductive wiring; and

a second barrier layer covering a top surface and the portion of the sidewall of the conductive wiring, wherein the second barrier layer does not extend over the dielectric layer.

2. The semiconductor structure of claim 1, wherein the first barrier layer comprises a metal that can be silicided.

3. The semiconductor structure of claim 2, wherein the metal comprises a material selected from the group consisting essentially of cobalt, nickel, and combinations thereof.

4. The semiconductor structure of claim 1, wherein the first barrier layer is free from cobalt and nickel.

5. The semiconductor structure of claim 1, wherein the conductive wiring comprises copper.

6. The semiconductor structure of claim 1, wherein the second barrier layer is a derivative of a carbon-based silane.

7. A semiconductor device comprising:

a conductive material embedded within a dielectric layer over a substrate, the conductive material being planar with the dielectric layer;

a first barrier layer between the conductive material and the dielectric layer, the first barrier layer being non-planar with the conductive material such that a first sidewall of the conductive material facing the dielectric layer is uncovered by the first barrier layer; and

a second barrier layer different from the first barrier layer, wherein the second barrier layer covers the first sidewall and covers a top surface of the conductive material but not a top surface of the dielectric layer.

8. The semiconductor device of claim 7, wherein the first barrier layer comprises a metal that can be silicided.

9. The semiconductor device of claim 8, wherein the metal comprises a material selected from the group consisting essentially of cobalt, nickel, and combinations thereof.

10. The semiconductor device of claim 7, wherein the first barrier layer is free from cobalt and nickel.

11. The semiconductor device of claim 7, wherein the conductive material comprises copper.

12. A semiconductor device comprising:

a dielectric material over a substrate;

a conductive material embedded within the dielectric material, wherein the conductive material has a first sidewall, the first sidewall comprising a first section and a second section;

a first barrier layer between the first section of the first sidewall and the dielectric material; and

a second barrier layer between the second section of the first sidewall and the dielectric material, wherein the second barrier layer is different from the first barrier layer and wherein the second barrier layer extends over a top surface of the conductive material but does not extend over a top surface of the dielectric material.

13. The semiconductor device of claim 12, wherein first barrier layer comprises a metal that can be silicided.

14. The semiconductor device of claim 13, wherein the metal comprises a material selected from the group consisting essentially of cobalt, nickel, and combinations thereof.

15. The semiconductor device of claim 12, wherein the first barrier layer is free from cobalt and nickel.

16. The semiconductor device of claim 12, wherein the conductive material comprises copper.

17. The semiconductor device of claim 12, wherein the second barrier layer is a derivative of a carbon-based silane.

18. The semiconductor device of claim 12, wherein the conductive material has a top surface that is planar with the dielectric material.

19. The semiconductor device of claim 12, wherein the second barrier layer is laterally separated from the dielectric material.

20. The semiconductor device of claim 12, wherein the second section of the first sidewall has a length that is greater than about 50 Å

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