Generation of voltage supply for low power digital circuit operation

• US 8,729,874 B2
• Filed: 06/06/2012
• Issued: 05/20/2014
• Est. Priority Date: 06/10/2011
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Ochoa, Agustin
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Pham, Emily P
• Application Number:
  US13/490,163
• Publication Number:
  US 20120313603A1
• Time in Patent Office: 713 Days
• Field of Search: 323/271, 330/288
• US Class Current: 323/271
• CPC Class Codes: G06K 19/0709 the source being an interrogation field

Abstract

A voltage regulator for low power operation of digital circuits includes an output node for providing a regulated output voltage, a diode-connected P-channel transistor in series with a second diode-connected N-channel transistor coupled between the output node and ground, and a bias current having a value for biasing the first and second diode-connected transistors in a sub-threshold mode of operation. The low power voltage regulator further includes a buffer amplifier or emitter or source follower stage to provide a low impedance regulated voltage. The bias current may be generated by a bandgap circuit.

Claims

1. A low power voltage regulator comprising:

a first diode-connected transistor of a first polarity type in series with a second diode-connected transistor of a second polarity type coupled between an output node and ground;

a first bias current having a value for biasing the first and second diode-connected transistors in a sub-threshold mode of operation; and

a buffer amplifier comprising an input transistor having a gate forming an input of the buffer amplifier coupled to the output node, a drain, and a source forming an output of the buffer amplifier for providing the regulated output voltage, a feedback transistor having a gate coupled to the drain of the input transistor, a source for coupling to a power supply voltage, and a drain coupled to the source of the input transistor, a second bias current coupled to the drain of the input transistor, and a third bias current coupled to the source of the input transistor.

2. The low power voltage regulator of claim 1 wherein the first diode-connected transistor comprises a P-channel transistor.

3. The low power voltage regulator of claim 1 wherein the second diode-connected transistor comprises an N-channel transistor.

4. The low power voltage regulator of claim 1 wherein the first bias current is generated by a bandgap circuit.

5. A method of providing a regulated output voltage comprising:

providing a first diode-connected transistor of a first polarity type in series with a second diode-connected transistor of a second polarity type coupled between an output node and ground; and

biasing with a first bias current the first and second diode-connected transistors in a sub-threshold mode of operation for low power operation; and

buffering the regulated output voltage with a buffer amplifier comprising an input transistor having a gate forming an input of the buffer amplifier coupled to the output node, a drain, and a source forming an output of the buffer amplifier for providing the regulated output voltage, a feedback transistor having a gate coupled to the drain of the input transistor, a source for coupling to a power supply voltage, and a drain coupled to the source of the input transistor, a second bias current coupled to the drain of the input transistor, and a third bias current coupled to the source of the input transistor.

6. The method of claim 5 wherein the first diode-connected transistor comprises a P-channel transistor.

7. The method of claim 5 wherein the second diode-connected transistor comprises An N-channel transistor.

8. A low power voltage regulator comprising:

a first diode-connected transistor of a first polarity type in series with a second diode-connected transistor of a second polarity type coupled between an output node and ground;

a first bias current having a value for biasing the first and second diode-connected transistors in a sub-threshold mode of operation;

a third transistor coupled between the first bias current and the first and second diode-connected transistors; and

a buffer amplifier coupled to the third transistor, the buffer amplifier comprising;

an input transistor having a gate forming an input of the buffer amplifier, a drain, and a source forming an output of the buffer amplifier for providing the regulated output voltage;

a feedback transistor having a gate coupled to the drain of the input transistor, a source for coupling to a power supply voltage, and a drain coupled to the source of the input ransistor;

a second bias current coupled to the drain of the input transistor; and

a third bias current coupled to the source of the input transistor.

9. The low power voltage regulator of claim 8 wherein the third bias current is greater than the second bias current.

10. The low power voltage regulator of claim 8 wherein the input transistor comprises an N-channel transistor.

11. The low power voltage regulator of claim 8 wherein the feedback transistor comprises a P-channel transistor.

12. The low power voltage regulator of claim 8 wherein the first diode-connected transistor comprises a P-channel transistor.

13. The low power voltage regulator of claim 8 wherein the second diode-connected transistor comprises an N-channel transistor.

14. The low power voltage regulator of claim 8 wherein the first bias current is generated by a bandgap circuit.