Phase locked loop and semiconductor device using the same

• US 8,729,938 B2
• Filed: 05/16/2012
• Issued: 05/20/2014
• Est. Priority Date: 05/20/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Watanabe, Kazunori
• Primary Examiner(s): COX, CASSANDRA F
• Application Number:
  US13/472,768
• Publication Number:
  US 20120293223A1
• Time in Patent Office: 734 Days
• Field of Search: None
• US Class Current: 327/156
• CPC Class Codes: H03L 3/00 Starting of generators
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump

Abstract

It is an object of the present invention to provide a phase locked loop in which a voltage signal input to a voltage controlled oscillator after a return from a stand-by state becomes constant in a short time and power consumption is reduced. A transistor including a semiconductor layer formed using an oxide semiconductor material is provided between an input terminal of a voltage controlled oscillator and a capacitor of a loop filter. The transistor is turned on in a normal operation state and turned off in a stand-by state.

Claims

1. A phase locked loop comprising a voltage controlled oscillator and a loop filter including a transistor and a capacitor electrically connected to the transistor,

wherein a channel formation region of the transistor comprises an oxide semiconductor material,

wherein the capacitor is configured to hold a potential when the transistor is off,

wherein the potential is input to the loop filter, and

wherein the transistor is configured to be turned off when a cycle of a periodic signal output from the voltage controlled oscillator is constant.

2. The phase locked loop according to claim 1, wherein the oxide semiconductor material comprises one or more of elements selected from In, Ga, Sn, and Zn.

3. The phase locked loop according to claim 1, wherein the transistor comprises:

a first insulating layer over a substrate;

a second insulating layer over the first insulating layer;

an oxide semiconductor layer over the first insulating layer and the second insulating layer, the oxide semiconductor layer comprising the channel formation region;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode over the oxide semiconductor layer with the gate insulating layer interposed therebetween; and

a pair of electrodes over the first insulating layer with the oxide semiconductor layer interposed therebetween,

wherein the second insulating layer overlaps with an end portion of the oxide semiconductor layer and is in contact with the pair of electrodes.

4. The phase locked loop according to claim 3, wherein the oxide semiconductor layer comprises one or more of elements selected from In, Ga, Sn, and Zn.

5. The phase locked loop according to claim 3,

wherein the oxide semiconductor layer comprises a first region and a second region surrounding the first region,

wherein the first region overlaps with the gate electrode, and

wherein a resistance of the first region is higher than a resistance of the second region.

6. A semiconductor device comprising the phase locked loop according to claim 1.

7. A semiconductor device comprising a phase locked loop including a voltage controlled oscillator and a loop filter comprising a transistor and a capacitor electrically connected to the transistor,

wherein a channel formation region of the transistor comprises an oxide semiconductor material,

wherein the phase locked loop is configured to become a stand-by state after the transistor is turned off,

wherein the phase locked loop is configured to be returned from the stand-by state after the transistor is turned on, and

wherein the transistor is configured to be turned off when a cycle of a periodic signal output from the voltage controlled oscillator is constant.

8. The semiconductor device according to claim 7, wherein the oxide semiconductor material comprises one or more of elements selected from In, Ga, Sn, and Zn.

9. The semiconductor device according to claim 7, wherein the transistor comprising:

a first insulating layer over a substrate;

a second insulating layer over the first insulating layer;

an oxide semiconductor layer over the first insulating layer and the second insulating layer, the oxide semiconductor layer comprising the channel formation region;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode over the oxide semiconductor layer with the gate insulating layer interposed therebetween; and

a pair of electrodes over the first insulating layer with the oxide semiconductor layer interposed therebetween,

wherein the second insulating layer overlaps with an end portion of the oxide semiconductor layer and is in contact with the pair of electrodes.

10. The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises one or more of elements selected from In, Ga, Sn, and Zn.

11. The semiconductor device according to claim 9,

wherein the oxide semiconductor layer comprises a first region and a second region surrounding the first region,

wherein the first region overlaps with the gate electrode, and

wherein a resistance of the first region is higher than a resistance of the second region.

12. A semiconductor device comprising a phase locked loop including:

a phase frequency detector configured to receive a first periodic signal and a second periodic signal and configured to output a third periodic signal corresponding to a phase difference between the first periodic signal and the second periodic signal;

a charge pump configured to receive the third periodic signal and configured to output a first analog signal corresponding to the third periodic signal;

a loop filter configured to receive the first analog signal and configured to output a second analog signal corresponding to the first analog signal; and

a voltage controlled oscillator configured to receive the second analog signal and configured to output a fourth periodic signal corresponding to the second analog signal,

wherein the loop filter comprises a transistor and a capacitor,

wherein a channel formation region of the transistor comprises an oxide semiconductor material,

wherein one of a source electrode and a drain electrode of the transistor is electrically connected to the charge pump and the voltage controlled oscillator,

wherein the other of the source electrode and the drain electrode of the transistor is electrically connected to the capacitor,

wherein the phase locked loop is configured to become a stand-by state after the transistor is turned off,

wherein the phase locked loop is configured to be returned from the stand-by state after the transistor is turned on, and

wherein the transistor is configured to be turned off when a cycle of the fourth periodic signal is constant.

13. The semiconductor device according to claim 12, further comprising a frequency divider configured to receive the fourth periodic signal and configured to output the first periodic signal corresponding to the fourth periodic signal.

14. The semiconductor device according to claim 12, wherein the oxide semiconductor material comprises one or more of elements selected from In, Ga, Sn, and Zn.

15. The semiconductor device according to claim 12, wherein the first periodic signal is formed by dividing the fourth periodic signal.

16. The semiconductor device according to claim 12, wherein the second analog signal is formed by smoothing the first analog signal.

17. The semiconductor device according to claim 12, wherein the voltage controlled oscillator is configured to output the fourth periodic signal to an output terminal.

18. The semiconductor device according to claim 12, wherein the loop filter is configured to output the second analog signal to an output terminal.

19. The semiconductor device according to claim 12, wherein the transistor comprising:

a first insulating layer over a substrate;

a second insulating layer over the first insulating layer;

an oxide semiconductor layer over the first insulating layer and the second insulating layer, the oxide semiconductor layer comprising the channel formation region;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode over the oxide semiconductor layer with the gate insulating layer interposed therebetween; and

a pair of electrodes over the first insulating layer with the oxide semiconductor layer interposed therebetween,

wherein the second insulating layer overlaps with an end portion of the oxide semiconductor layer and is in contact with the pair of electrodes.

20. The semiconductor device according to claim 19, wherein the oxide semiconductor layer comprises one or more of elements selected from In, Ga, Sn, and Zn.

21. The semiconductor device according to claim 19,

wherein the oxide semiconductor layer comprises a first region and a second region surrounding the first region,

wherein the first region overlaps with the gate electrode, and

wherein a resistance of the first region is higher than a resistance of the second region.