Charging/discharging circuit and PLL circuit using the same

• US 8,729,939 B2
• Filed: 08/21/2013
• Issued: 05/20/2014
• Est. Priority Date: 10/17/2012
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MStar Semiconductor Incorporated (MediaTek, Inc.)
• Inventors: Hsieh, Yi Chang
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/971,963
• Publication Number:
  US 20140103975A1
• Time in Patent Office: 272 Days
• Field of Search: 327/148, 327/157
• US Class Current: 327/157
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence

Abstract

A charging/discharging circuit includes a connection terminal, a reference current providing module, an up current module and a down current module. The down current module includes: a first switch module, having a first control terminal, for receiving the down signal to determine whether the first switch module is turned on; a first bias transistor, having a first terminal coupled to the connection terminal, a second terminal coupled to the first switch module, and a control terminal coupled to the reference current providing module; and a first capacitor simulation transistor, having a first terminal and a second terminal coupled to the control terminal of the first switch module, and a control terminal coupled to the control terminal of the first bias transistor.

Claims

1. A charging/discharging circuit, for charging/discharging a target element, comprising:

a connection terminal, coupled to a target element, wherein the charging/discharging circuit provides an up current to the target element via the connection terminal and draws a down current from the target element via the connection terminal;

a reference current providing module, for providing a reference current;

an up current module, controlled by an up signal and providing said up current according to said reference current; and

a down current module, controlled by a down signal and drawing said down current according to said reference current, comprising;

a first switch module, having a first switch module control terminal for receiving said down signal;

a first bias transistor, comprising;

a first bias transistor first terminal, coupled to said connection terminal;

a first bias transistor second terminal, coupled to said first switch module; and

a first bias transistor control terminal, coupled to said reference current providing module; and

a first capacitor simulation transistor, comprising;

a first capacitor simulation transistor first terminal, coupled to said first switch module control terminal;

a first capacitor simulation transistor second terminal, coupled to said first switch module control terminal; and

a first capacitor simulation transistor control terminal, coupled to said first bias transistor control terminal.

2. The charging/discharging circuit according to claim 1, wherein the first switch module comprises:

a first switch element, comprising;

a first switch first terminal, coupled to a first predetermined voltage;

a first switch second terminal, coupled to said first bias second terminal; and

a first switch control terminal, receiving said down signal; and

a second switch element, comprising;

a second switch first terminal, coupled to said first switch second terminal;

a second switch second terminal, coupled to a second predetermined voltage; and

a second switch control terminal coupled to said first switch control terminal and receiving said down signal.

3. The charging/discharging circuit according to claim 1, wherein said first capacitor simulation transistor is in a fully turned on state when said first switch module is turned on by said down signal.

4. The charging/discharging circuit according to claim 1, wherein said first bias transistor and said first capacitor simulation transistor have the same transistor specifications.

5. The charging/discharging circuit according to claim 1, wherein said first bias transistor is an N-type metal oxide semiconductor (MOS) transistor and said first capacitor simulation transistor is an N-type metal oxide semiconductor (MOS) transistor.

6. The charging/discharging circuit according to claim 1, wherein said reference current providing module is a current mirror, and said first bias transistor utilizes said reference current mapped from said reference current providing module as said down current.

7. The charging/discharging circuit according to claim 1, wherein said up current module comprises:

a second switch module, having a second switch module control terminal coupled to said second switch control terminal for receiving said up signal;

a second bias transistor, comprising;

a second bias transistor first terminal, coupled to said connection terminal;

a second bias transistor second terminal, coupled to said second switch module; and

a second bias transistor control terminal, coupled to said reference current providing module; and

a second capacitor simulation transistor, comprising;

a second capacitor simulation transistor first terminal, coupled to said second switch module control terminal;

a second capacitor simulation transistor second terminal, coupled to said second switch control terminal; and

a second capacitor simulation transistor control terminal, coupled to said second bias control terminal.

8. The charging/discharging circuit according to claim 7, wherein said second switch module comprises:

a first switch element, comprising;

a first switch second terminal, coupled to a first predetermined voltage;

a first switch first terminal, coupled to said second bias second terminal; and

a first switch control terminal, receiving said up signal; and

a second switch element, comprising;

a second switch second terminal, coupled to said first switch first terminal;

a second switch first terminal, coupled to a second predetermined voltage; and

a second switch control terminal, coupled to said first switch control terminal and receiving said up signal.

9. The charging/discharging circuit according to claim 7, wherein said second capacitor simulation transistor is in a fully turned on state when said second switch module is turned on by said up signal.

10. The charging/discharging circuit according to claim 7, wherein said second bias transistor and said second capacitor simulation transistor have same transistor specifications.

11. The charging/discharging circuit according to claim 7, wherein said second bias transistor is a P-type metal oxide semiconductor (MOS) transistor, and said second capacitor simulation transistor is a P-type metal oxide semiconductor (MOS) transistor.

12. A charging/discharging circuit, for charging/discharging a target element, comprising:

a connection terminal, coupled to a target element, wherein the charging/discharging circuit provides an up current to the target element via the connection terminal and draws a down current from the target element via the connection terminal;

a reference current providing module, for providing a reference current;

a down current module, controlled by a down signal and drawing said down current according to said reference current; and

an up current module, controlled by an up signal and providing said up current according to said reference current, comprising;

a switch module, having a switch module control terminal for receiving said up signal;

a bias transistor, comprising;

a bias transistor first terminal, coupled to said connection terminal;

a bias transistor second terminal, coupled to said switch module; and

a bias transistor control terminal, coupled to said reference current providing module; and

a capacitor simulation transistor, comprising;

a capacitor simulation transistor first terminal, coupled to said switch module control terminal;

a capacitor simulation transistor second terminal, coupled to said switch module control terminal; and

a capacitor simulation transistor control terminal, coupled to said bias control terminal.

13. The charging/discharging circuit according to claim 12, wherein said switch module comprises:

a first switch element, comprising;

a first switch second terminal, coupled to a first predetermined voltage;

a first switch first terminal, coupled to said bias second terminal; and

a first switch control terminal, receiving said up signal; and

a second switch element, comprising;

a second switch second terminal, coupled to said first switch first terminal;

a second switch first terminal, coupled to a second predetermined voltage; and

a second switch control terminal, coupled to said first switch control terminal and receiving said up signal.

14. The charging/discharging circuit according to claim 12, wherein said capacitor simulation transistor is in a fully turned on state when said switch module is turned on by said up signal.

15. The charging/discharging circuit according to claim 12, wherein said bias transistor and said capacitor simulation transistor have the same transistor specifications.

16. The charging/discharging circuit according to claim 12, wherein said bias transistor is a P-type metal oxide semiconductor (MOS) transistor, and said capacitor simulation transistor is a P-type metal oxide semiconductor (MOS) transistor.

17. The charging/discharging circuit according to claim 12, wherein said reference current providing module is a current mirror, and said bias transistor utilizes said reference current mapped from said reference current providing module as said up current.

18. A phase-locked loop (PLL) circuit, comprising:

a phase detector, for comparing phases of a reference signal and an output signal to generate an up signal or a down signal;

a loop filter;

a charge pump, for charging or discharging said loop filter such that said loop filter generates a control voltage, generating an up current to charge said loop filter when receiving said up signal, and drawing a down current from said loop filter to discharge said loop filter when receiving said down signal; and

a voltage-controlled oscillator (VCO), receiving said control voltage to generate said output signal;

wherein, said charge pump comprises;

a connection terminal, coupled to said loop filter, wherein the charging/discharging circuit provides said up current to said loop filter via the connection terminal and draws said down current from said loop filter via the connection terminal;

a reference current providing module, for providing a reference current;

an up current module, controlled by said up signal and providing said up current according to said reference current; and

a down current module, controlled by said down signal and drawing said down current according to said reference current, comprising;

a first switch module, having a first switch module control terminal, receiving said down signal at the first switch module control terminal;

a first bias transistor, comprising;

a first bias transistor first terminal, coupled to said connection terminal;

a first bias transistor second terminal coupled to said first switch module; and

a first bias transistor control terminal, coupled to said reference current providing module; and

a first capacitor simulation transistor, comprising;

a first capacitor simulation transistor first terminal, coupled to said first switch module control terminal;

a first capacitor simulation transistor second terminal, coupled to said first switch module control terminal; and

a first capacitor simulation transistor control terminal coupled to said first bias control terminal.

19. The PLL circuit according to claim 18, wherein the first switch module comprises:

a first switch element, comprising;

a first switch first terminal, coupled to a first predetermined voltage;

a first switch second terminal, coupled to said first bias second terminal; and

a first switch control terminal, receiving said down signal; and

a second switch element, comprising;

a second switch first terminal, coupled to said first switch second terminal;

a second switch second terminal, coupled to a second predetermined voltage; and

a second switch control terminal coupled to said first switch control terminal and receiving said down signal.

20. The PLL circuit according to claim 18, wherein said first capacitor simulation transistor is in a fully turned on state when said first switch module is turned on by said down signal.

21. The PLL circuit according to claim 18, wherein said first bias transistor and said first capacitor simulation transistor have same transistor specifications.

22. The PLL circuit according to claim 18, wherein said first bias transistor is an N-type metal oxide semiconductor (MOS) transistor, and said first capacitor simulation transistor is an N-type metal oxide semiconductor (MOS) transistor.

23. The PLL circuit according to claim 18, wherein said reference current providing module is a current mirror, and said first bias transistor utilizes said reference current mapped from said reference current providing module as said down current.

24. The PLL circuit according to claim 18, wherein said up current module comprises:

a second switch module, having a second switch module control terminal receiving said up signal at said second switch module control terminal to determine whether the second switch module is turned on;

a second bias transistor, comprising;

a second bias transistor first terminal coupled to said connection terminal;

a second bias transistor second terminal, coupled to said second switch module; and

a second bias transistor control terminal, coupled to said reference current providing module; and

a second capacitor simulation transistor, comprising;

a second capacitor simulation transistor first terminal, coupled to said second switch module control terminal;

a second capacitor simulation transistor second terminal, coupled to said second switch module control terminal; and

a second capacitor simulation transistor control terminal, coupled to said second bias control terminal.

25. The PLL circuit according to claim 24, wherein said second switch module comprises:

a first switch element, comprising;

a first switch second terminal, coupled to a first predetermined voltage;

a first switch first terminal, coupled to said second bias second terminal; and

a first switch control terminal, receiving said up signal; and

a second switch element, comprising;

a second switch second terminal, coupled to said first switch first terminal;

a second switch first terminal, coupled to a second predetermined voltage; and

a second switch control terminal, coupled to said first switch control terminal and receiving said up signal.

26. The PLL circuit according to claim 24, wherein said second capacitor simulation transistor is in a fully turned on state when said second switch module is turned on by said up signal.

27. The PLL circuit according to claim 24, wherein said second bias transistor and said second capacitor simulation transistor have same transistor specifications.

28. The PLL circuit according to claim 24, wherein said second bias transistor is a P-type metal oxide semiconductor (MOS) transistor, and said second capacitor simulation transistor is a P-type metal oxide semiconductor (MOS) transistor.

29. A PLL circuit, comprising:

a phase detector, for comparing phases of a reference signal and an output signal to generate an up signal or a down signal;

a loop filter;

a charge pump, charging/discharging said loop filter for enabling said loop filter to generate a control voltage, generating an up current to charge said loop filter when receiving said up signal, and drawing a down current from said loop filter to discharge the loop filter when receiving said down signal; and

a VCO, receiving said control voltage to generate said output signal;

wherein, said charge pump comprises;

a connection terminal, coupled to said loop filter, wherein the charging/discharging circuit provides said up current to said loop filter via the connection terminal and draws said down current from said loop filter via the connection terminal;

a reference current providing module, for providing a reference current;

a down current module, controlled by said down signal and drawing said down current according to said reference current; and

an up current module, controlled by said up signal and providing said up current according to said reference current, comprising;

a switch module, having a switch module control terminal, receiving said up signal at the switch module control terminal to determine whether the switch module is turned on;

a bias transistor, comprising;

a bias transistor first terminal, coupled to said connection terminal;

a bias transistor second terminal coupled to said switch module; and

a bias transistor control terminal coupled to said reference current providing module; and

a capacitor simulation transistor, comprising;

a capacitor simulation transistor first terminal, coupled to the said switch module control terminal;

a capacitor simulation transistor second terminal, coupled to said switch module control terminal; and

a capacitor simulation transistor control terminal, coupled to said bias control terminal.

30. The PLL circuit according to claim 29, wherein said switch module comprises:

a first switch element, comprising;

a first switch second terminal, coupled to a first predetermined voltage;

a first switch first terminal, coupled to said bias second terminal; and

a first switch control terminal, receiving said up signal; and

a second switch element, comprising;

a second switch second terminal, coupled to said first switch first terminal;

a second switch first terminal, coupled to a second predetermined voltage; and

a second switch control terminal, coupled to said first switch control terminal and receiving the said signal.

31. The PLL circuit according to claim 29, wherein said capacitor simulation transistor is in a fully turned on state when said switch module is turned on by said up signal.

32. The PLL circuit according to claim 29, wherein said bias transistor and said capacitor simulation transistor have same transistor specifications.

33. The PLL circuit according to claim 29, wherein said bias transistor is a P-type metal oxide semiconductor (MOS) transistor, and said capacitor simulation transistor is a P-type metal oxide semiconductor (MOS) transistor.

34. The PLL circuit according to claim 29, wherein said reference current providing module is a current mirror, and said bias transistor utilizes said reference current mapped from said reference current providing module as said up current.