Double data rate serial encoder
First Claim
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1. A method for serial encoding, comprising:
- providing a glitch-less multiplexer (mux) having a plurality of mux data inputs, a plurality of select inputs and a mux output, wherein the mux output does not glitch due to a change of any single select input bit;
providing a plurality of latches, having latch data inputs and latch data outputs, wherein the latch data outputs are coupled to the plurality of mux data inputs;
providing an enabler, coupled to the latches;
providing a counter, coupled to the select inputs of the mux, wherein the counter transitions on either a rising or a falling edge of an input clock, and only a single counter state bit changes on a transition between any two consecutive states in a count sequence;
employing the enabler to enable and control the latches to update the latch data outputs at a time when the latch data inputs are not changing; and
employing the counter to select one of the plurality of mux data inputs in a predetermined sequence for the mux output and control the enabler.
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Abstract
A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.
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Citations
28 Claims
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1. A method for serial encoding, comprising:
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providing a glitch-less multiplexer (mux) having a plurality of mux data inputs, a plurality of select inputs and a mux output, wherein the mux output does not glitch due to a change of any single select input bit; providing a plurality of latches, having latch data inputs and latch data outputs, wherein the latch data outputs are coupled to the plurality of mux data inputs; providing an enabler, coupled to the latches; providing a counter, coupled to the select inputs of the mux, wherein the counter transitions on either a rising or a falling edge of an input clock, and only a single counter state bit changes on a transition between any two consecutive states in a count sequence; employing the enabler to enable and control the latches to update the latch data outputs at a time when the latch data inputs are not changing; and employing the counter to select one of the plurality of mux data inputs in a predetermined sequence for the mux output and control the enabler. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for serial encoding, comprising:
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storing a plurality of input bits; generating an input selection sequence by employing a counter that transitions on either a rising or a falling edge of an input clock, and for which a single counter state bit to change on a transition between any two consecutive states in a count sequence; and outputting serially said plurality of input bits according to said input selection sequence, wherein outputting serially includes outputting serially without glitches during input transitions in said input selection sequence. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A non-transitory computer program product, comprising:
- computer readable medium comprising;
code for causing serial encoding by employing; a glitch-less multiplexer (mux) having a plurality of mux data inputs, a plurality of select inputs and a mux output, wherein the mux output does not glitch due to a change of any single select input bit; a plurality of latches, having latch data inputs and latch data outputs, wherein the latch data outputs are coupled to the plurality of mux data inputs; an enabler, coupled to the latches; a counter, coupled to the select inputs of the mux, wherein the counter transitions on either a rising or a falling edge of an input clock, and only a single counter state bit changes on a transition between any two consecutive states in a count sequence, the code comprising; code for causing the enabler to enable and control the latches to update the latch data outputs at a time when the latch data inputs are not changing; and code for causing the counter to select one of the plurality of mux data inputs in a predetermined sequence for the mux output and control the enabler. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
- computer readable medium comprising;
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23. A non-transitory computer readable medium comprising:
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code for causing serial encoding, the computer code comprising; code for causing a plurality of inputs bits to be stored; code for causing an input selection sequence to be generated by employing a counter that transitions on either a rising or a falling edge of an input clock, and for which a single counter state bit changes on a transition between any two consecutive states in a count sequence; and code for causing said plurality of input bits to be output serially according to said input selection sequence, wherein outputting serially includes outputting serially without glitches during input transitions in said input selection sequence. - View Dependent Claims (24, 25, 26, 27, 28)
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Specification