Parallel array architecture for a graphics processor

• US 8,730,249 B2
• Filed: 10/07/2011
• Issued: 05/20/2014
• Est. Priority Date: 12/19/2005
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Danskin, John M., Montrym, John S., Lindholm, John Erik, Molnar, Steven E., French, Mark
• Primary Examiner(s): McDowell, Jr., Maurice L
• Assistant Examiner(s): Ricks, Donna J
• Application Number:
  US13/269,462
• Publication Number:
  US 20120026171A1
• Time in Patent Office: 956 Days
• Field of Search: None
• US Class Current: 345/505
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2210/52 Parallel processing
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 2360/122 Tiling
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.

Claims

1. A graphics processor comprising:

a multithreaded core array including a plurality of processing clusters; and

a crossbar configured to connect the plurality of processing clusters to a frame buffer configured to store data associated with pixels of an image, the frame buffer being partitioned into a plurality of partitions,

wherein each processing cluster includes;

at least one processing core operable to execute programs;

a pixel module configured to receive coverage data and to direct at least one of the processing cores to execute a pixel shader program on the received coverage data to generate pixel values; and

a raster operations unit configured to receive the pixel values generated by the at least one processing core included in the same processing cluster as the raster operations unit and to update the pixel data stored in the frame buffer based on the received pixel values, and

wherein the raster operations unit of each processing cluster is coupled to the crossbar such that every partition of the frame buffer is accessible to every one of the raster operations units.

2. The graphics processor of claim 1 wherein the number of partitions of the frame buffer is different from the number of raster operations units.

3. The graphics processor of claim 1 wherein the number of partitions of the frame buffer is equal to the number of raster operations units.

4. The graphics processor of claim 1 wherein each processing cluster further includes a geometry module configured to receive vertex data and to direct at least one of the processing cores to execute at least one of a vertex shader program or a geometry shader program on the received vertex data.

5. A graphics processor comprising:

a multithreaded core array including a plurality of processing clusters;

a rasterizer configured to generate coverage data for each of a plurality of pixels;

pixel distribution logic configured to deliver a portion of the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array; and

a crossbar connecting the plurality of processing clusters to a frame buffer configured to store pixels of an image, the frame buffer being partitioned into a plurality of partitions,

wherein each processing cluster includes;

at least one processing core operable to execute program instructions;

a pixel module configured to receive a portion of the coverage data from the rasterizer and to direct at least one of the processing cores to execute a pixel shader program on the received coverage data to generate pixel values; and

a raster operations unit configured to receive the pixel values generated by the at least one processing core included in the same processing cluster as the raster operations unit and to combine the received pixel values with pixels of an image in the frame buffer, and

wherein the raster operations unit of each processing cluster is coupled to the crossbar such that every partition of the frame buffer is accessible to every one of the raster operations units.

6. The graphics processor of claim 5 wherein the number of partitions of the frame buffer is different from the number of raster operations units.

7. The graphics processor of claim 5 wherein the number of partitions of the frame buffer is equal to the number of raster operations units.

8. The graphics processor of claim 5 wherein each processing cluster further includes a geometry module configured to receive vertex data and to direct at least one of the processing cores to execute at least one of a vertex shader program or a geometry shader program on the received vertex data.

9. The graphics processor of claim 5 wherein the image area is divided into a plurality of tiles, each tile being assigned to one of the processing clusters, and wherein the pixel distribution logic selects the one of the processing clusters based on a determination as to which of the plurality of tiles includes the first pixel.

10. The graphics processor of claim 9 wherein at least two of the plurality of tiles are assigned to each of the processing clusters, wherein for each processing cluster, the tiles assigned thereto are not contiguous with each other.

11. A graphics processor comprising:

a multithreaded core array including a plurality of processing clusters; and

a crossbar configured to connect the plurality of processing clusters to a plurality of frame buffers, each of the plurality of frame buffers being configured to store data for a different attribute associated with pixels of an image, each of the plurality of frame buffers being partitioned into a plurality of partitions,

wherein each processing cluster includes;

at least one processing core operable to execute programs;

a pixel module configured to receive coverage data and to direct at least one of the processing cores to execute a pixel shader program on the received coverage data to generate pixel values; and

a raster operations unit configured to receive the pixel values generated by the at least one processing core included in the same processing cluster as the raster operations unit and to update the pixel data stored in the one or more frame buffers based on the received pixel values, and

wherein the raster operations unit of each processing cluster is coupled to the crossbar such that every partition of each one of the frame buffers is accessible to every one of the raster operations units.

12. The graphics processor of claim 11 wherein the plurality of frame buffers includes a first frame buffer configured to store Z data for the pixels of the image and a second frame buffer configured to store color data for the pixels of the image.

13. The graphics processor of claim 12 wherein the first frame buffer is partitioned into a first number of partitions and the second frame buffer is partitioned into a second number of partitions, wherein the first number and the second number are different.

14. The graphics processor of claim 12 wherein the first frame buffer and the second frame buffer are each partitioned into a same number of partitions.

15. The graphics processor of claim 11 wherein each processing cluster further includes a geometry module configured to receive vertex data and to direct at least one of the processing cores to execute at least one of a vertex shader program or a geometry shader program on the received vertex data.

16. The graphics processor of claim 11 wherein the plurality of frame buffers includes a first frame buffer partitioned into a first number of partitions and a second frame buffer partitioned into a second number of partitions, wherein the first number and the second number are different.

17. The graphics processor of claim 11 wherein the plurality of frame buffers includes a first frame buffer a second frame buffer and wherein the first frame buffer and the second frame buffer are each partitioned into a same number of partitions.