EEPROM cell with transfer gate

• US 8,730,728 B2
• Filed: 09/13/2012
• Issued: 05/20/2014
• Est. Priority Date: 04/26/2012
• Status: Expired due to Fees

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Kang, Jin-Yeong
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US13/614,282
• Publication Number:
  US 20130286740A1
• Time in Patent Office: 614 Days
• Field of Search: 365/185.11, 365/185.24
• US Class Current: 365/185.11
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/045 Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

An EEPROM cell including a transfer gate that can suppress a data disturbance phenomenon of the EEPROM cell is provided. The EEPROM cell includes: an inverter; a control plate; a tunneling plate; a data output metal oxide semiconductor field effect transistor (MOSFET) that is connected to the inverter; a floating plate that is connected to the inverter; a tunneling capacitor area that is formed between the floating plate and the tunneling plate; and a transfer gate that is connected to the tunneling plate. As the transfer gate is added between a bit line and the tunneling plate of the EEPROM cell, in a standby (or unselected) operation of the EEPROM cell, the tunneling plate is floated.

Claims

1. An EEPROM cell, comprising:

an inverter;

a tunneling plate;

a data output metal oxide semiconductor field effect transistor (MOSFET) that is connected to the inverter;

a floating plate that is connected to the inverter;

a tunneling capacitor area that is formed between the floating plate and the tunneling plate; and

a transfer gate that is connected to the tunneling plate,

wherein the transfer gate transfers an operation voltage of the EEPROM cell that is applied to a bit line of the EEPROM cell to the tunneling plate.

2. The EEPROM cell of claim 1, wherein the inverter is a CMOS inverter, and a gate of the CMOS inverter is connected to the floating plate.

3. The EEPROM cell of claim 1, further comprising:

a control plate that is connected to a word line of the EEPROM cell; and

a control capacitor area that is formed between the control plate and the floating plate.

4. The EEPROM cell of claim 3, wherein a capacity of a capacitor that is formed in the tunneling capacitor area is 1%-10% of that of a capacitor that is formed in the control capacitor area.

5. The EEPROM cell of claim 1, wherein the transfer gate comprises a p-MOSFET and an n-MOSFET, and

a drain of the p-MOSFET and a drain of the n-MOSFET are connected to the tunneling plate, while a source of the p-MOSFET and a source of the n-MOSFET are connected to a bit line.

6. The EEPROM cell of claim 1, wherein the transfer gate comprises a p-MOSFET and an n-MOSFET, and

a source of the p-MOSFET and a source of the n-MOSFET are connected to the tunneling plate, while a drain of the p-MOSFET and a drain of the n-MOSFET are connected to a bit line.

7. The EEPROM cell of claim 5, wherein the transfer gate comprises:

an n-type well that is doped with donor;

a p-type well that is doped with acceptor; and

a deep n-type well that separates the p-type well from a p-type substrate of the transfer gate.

8. The EEPROM cell of claim 7, wherein a maximum value of a programming or erasing operation voltage of the EEPROM cell is applied to the n-type well of the transfer gate, a minimum value of a programming or erasing operation voltage of the EEPROM cell is applied to the p-type well, and the deep n-type well is grounded.

9. The EEPROM cell of claim 5, wherein a gate of the p-MOSFET and a gate of the n-MOSFET are commonly grounded.

10. A method of suppressing a data disturbance phenomenon of an EEPROM cell comprising an inverter, a tunneling plate, a data output MOSFET that is connected to the inverter, a floating plate that is connected to the inverter, a tunneling capacitor area that is formed between the floating plate and the tunneling plate, and a transfer gate that is connected to the tunneling plate, the method comprising:

intercepting a voltage that is transferred to the tunneling plate by the transfer gate;

floating a voltage of the tunneling plate within a predetermined voltage range; and

increasing or decreasing the voltage of the floated tunneling plate according to a voltage of the floating plate in order to reduce a difference between the voltage of the floated tunneling plate and a voltage of the floating plate.

11. The method of claim 10, wherein the intercepting a voltage that is transferred to the tunneling plate by the transfer gate if the EEPROM cell is in standby mode, sense mode or unselected mode.