Systems and methods for averaging error rates in non-volatile devices and storage systems

• US 8,730,729 B2
• Filed: 11/21/2011
• Issued: 05/20/2014
• Est. Priority Date: 10/15/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: DensBits Technologies Ltd. (Broadcom, Inc.)
• Inventors: Weingarten, Hanan
• Primary Examiner(s): Graham, Kretelia
• Application Number:
  US13/301,308
• Publication Number:
  US 20120066441A1
• Time in Patent Office: 911 Days
• Field of Search: 36518501-18533
• US Class Current: 365/185.12
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H04L 1/203 Details of error rate determination, e.g. BER, FER or WER

Abstract

A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

Claims

1. A flash memory accessory device operative in conjunction with a data source supplying a stream of logical pages including data and a flash memory system including a multiplicity of physical pages, the flash memory accessory device comprising:

a page multiplexer and interleaver for;

(a) receiving multiple (J) encoded logical pages;

(b) breaking down each encoded logical page into multiple (J) logical pagelets;

(c) for each value of index i that ranges between 1 and J and for each value of index j that ranges between 1 and J, ordering an [(i+j−

2 moduloJ)+1]'"'"'th pagelet of an j'"'"'th logical page to an i'"'"'th pagelet of a j'"'"'th physical page of the multiplicity of physical pages.

2. A method for facilitating interaction between a data source supplying a stream of logical pages including data and a flash memory system including a multiplicity of physical pages, the method comprising:

receiving multiple (J) encoded logical pages;

breaking down each encoded logical page into multiple (J) logical pagelets;

ordering, for each value of index i that ranges between 1 and J and for each value of index j that ranges between 1 and J, an [(i+j−

2 moduloJ)+1]'"'"'th pagelet of an j'"'"'th logical page to an i'"'"'th pagelet of a j'"'"'th physical page of the multiplicity of physical pages.

3. A non-transitory computer useable medium having computer readable program code embodied for:

facilitating interaction between a data source supplying a stream of logical pages including data and a flash memory system including a multiplicity of physical pages, by;

receiving multiple (J) encoded logical pages;

breaking down each encoded logical page into multiple (J) logical pagelets;

ordering, for each value of index i that ranges between 1 and J and for each value of index j that ranges between 1 and J, an [(i+j−

2 moduloJ)+1]'"'"'th pagelet of an j'"'"'th logical page to an i'"'"'th pagelet of a j'"'"'th physical page of the multiplicity of physical pages.