Temporary storage circuit, storage device, and signal processing circuit

• US 8,730,730 B2
• Filed: 01/24/2012
• Issued: 05/20/2014
• Est. Priority Date: 01/26/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Yamazaki, Shunpei
• Primary Examiner(s): Lam, David
• Application Number:
  US13/356,726
• Publication Number:
  US 20120188815A1
• Time in Patent Office: 847 Days
• Field of Search: 365/189.05, 365/194, 365/154, 365/185.12, 365/185.03
• US Class Current: 365/185.12
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers

Abstract

A temporary storage circuit including a reduced number of transistors is provided. The temporary storage circuit includes storage elements, each of which includes a first transistor and a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A signal potential corresponding to data is input to a gate of the second transistor through the first transistor which is turned on by a control signal input to a gate of the first transistor. Then, the first transistor is turned off by a control signal input to the gate of the first transistor, so that the signal potential is held in the gate of the second transistor. When one of a source and a drain of the second transistor is set to a first potential, the state between the source and the drain of the second transistor is detected, whereby the data is read out.

Claims

1. A semiconductor device comprising:

a first storage circuit comprising a storage element comprising a first transistor; and

a second storage circuit,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor,

wherein the first storage circuit is configured to store first data and output the first data,

wherein the second storage circuit is configured to store the first data after the first storage circuit outputs the first data,

wherein the first storage circuit is configured to hold the first data after supply of power supply voltage to the first storage circuit is stopped, and

wherein the first storage circuit is configured to hold the first data after the supply of power supply voltage to the first storage circuit is restarted.

2. The semiconductor device according to claim 1,

wherein the storage element comprises a second transistor, and

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor.

3. The semiconductor device according to claim 1,

wherein the storage element comprises a second transistor and a capacitor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor and a first terminal of the capacitor.

4. The semiconductor device according to claim 1,

wherein the second storage circuit comprises a first block comprising a word line and a plurality of memory cells electrically connected to the word line, and

wherein the first storage circuit is configured to store data corresponding to the plurality of memory cells.

5. The semiconductor device according to claim 1,

wherein the storage element comprises a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein the storage element is configured to store data when a first voltage is supplied to a gate of the first transistor and a second voltage is supplied to a second terminal of the first transistor,

wherein the storage element is configured to hold the data while a third voltage is supplied to the gate of the first transistor, and

wherein the storage element is configured to output the data while a fourth voltage is supplied to a first terminal of the second transistor.

6. The semiconductor device according to claim 1,

wherein the storage element comprises a second transistor and a capacitor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor and a first terminal of the capacitor,

wherein the storage element is configured to store data when a first voltage is supplied to a gate of the first transistor and a second voltage is supplied to a second terminal of the first transistor,

wherein the storage element is configured to hold the data while a third voltage is supplied to the gate of the first transistor, and

wherein the storage element is configured to output the data while a fourth voltage is supplied to a first terminal of the second transistor and a fifth voltage is supplied to a second terminal of the capacitor.

7. The semiconductor device according to claim 1,

wherein the storage element comprises a capacitor,

wherein a first terminal of the first transistor is electrically connected to a first terminal of the capacitor,

wherein the storage element is configured to store data when a first voltage is supplied to a gate of the first transistor and a second voltage is supplied to a second terminal of the first transistor,

wherein the storage element is configured to hold the data while a third voltage is supplied to the gate of the first transistor, and

wherein the storage element is configured to output the data while a fourth voltage is supplied to the gate of the first transistor.

8. A semiconductor device comprising:

a first storage circuit comprising a storage element comprising a first transistor; and

a second storage circuit,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor,

wherein the first storage circuit is configured to store first data and output the first data,

wherein the second storage circuit is configured to store the first data after the first storage circuit outputs the first data and output second data,

wherein the first storage circuit is configured to store the second data after the second storage circuit outputs the second data and configured to output the second data,

wherein the first storage circuit is configured to hold the first data after supply of power supply voltage to the first storage circuit is stopped, and

wherein the first storage circuit is configured to hold the first data after the supply of power supply voltage to the first storage circuit is restarted.

9. The semiconductor device according to claim 8,

wherein the storage element comprises a second transistor, and

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor.

10. The semiconductor device according to claim 8,

wherein the storage element comprises a second transistor and a capacitor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor and a first terminal of the capacitor.

11. The semiconductor device according to claim 8,

wherein the second storage circuit comprises a first block comprising a word line and a plurality of memory cells electrically connected to the word line, and

wherein the first storage circuit is configured to store data corresponding to the plurality of memory cells.

12. The semiconductor device according to claim 8,

wherein the storage element comprises a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein the storage element is configured to store data when a first voltage is supplied to a gate of the first transistor and a second voltage is supplied to a second terminal of the first transistor,

wherein the storage element is configured to hold the data while a third voltage is supplied to the gate of the first transistor, and

wherein the storage element is configured to output the data while a fourth voltage is supplied to a first terminal of the second transistor.

13. The semiconductor device according to claim 8,

wherein the storage element comprises a second transistor and a capacitor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor and a first terminal of the capacitor,

wherein the storage element is configured to store data when a first voltage is supplied to a gate of the first transistor and a second voltage is supplied to a second terminal of the first transistor,

wherein the storage element is configured to hold the data while a third voltage is supplied to the gate of the first transistor, and

wherein the storage element is configured to output the data while a fourth voltage is supplied to a first terminal of the second transistor and a fifth voltage is supplied to a second terminal of the capacitor.

14. The semiconductor device according to claim 8,

wherein the storage element comprises a capacitor,

wherein a first terminal of the first transistor is electrically connected to a first terminal of the capacitor,

wherein the storage element is configured to store data when a first voltage is supplied to a gate of the first transistor and a second voltage is supplied to a second terminal of the first transistor,

wherein the storage element is configured to hold the data while a third voltage is supplied to the gate of the first transistor, and

wherein the storage element is configured to output the data while a fourth voltage is supplied to the gate of the first transistor.

15. A semiconductor device comprising:

a first storage circuit comprising a storage element comprising a first transistor; and

a second storage circuit,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor,

wherein the first storage circuit is configured to store first data and output the first data,

wherein the second storage circuit is configured to store the first data after the first storage circuit outputs the first data and output second data,

wherein the first storage circuit is configured to store the second data after the second storage circuit outputs the second data and configured to output the second data,

wherein the second storage circuit is configured to store the second data after the first storage circuit outputs the second data,

wherein the first storage circuit is configured to hold the first data after supply of power supply voltage to the first storage circuit is stopped, and

wherein the first storage circuit is configured to hold the first data after the supply of power supply voltage to the first storage circuit is restarted.

16. The semiconductor device according to claim 15,

wherein the storage element comprises a second transistor, and

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor.

17. The semiconductor device according to claim 15,

wherein the storage element comprises a second transistor and a capacitor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor and a first terminal of the capacitor.

18. The semiconductor device according to claim 15,

wherein the second storage circuit comprises a first block comprising a word line and a plurality of memory cells electrically connected to the word line, and

wherein the first storage circuit is configured to store data corresponding to the plurality of memory cells.

19. The semiconductor device according to claim 15,

wherein the storage element comprises a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein the storage element is configured to store data when a first voltage is supplied to a gate of the first transistor and a second voltage is supplied to a second terminal of the first transistor,

wherein the storage element is configured to hold the data while a third voltage is supplied to the gate of the first transistor, and

wherein the storage element is configured to output the data while a fourth voltage is supplied to a first terminal of the second transistor.

20. The semiconductor device according to claim 15,

wherein the storage element comprises a second transistor and a capacitor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor and a first terminal of the capacitor,

wherein the storage element is configured to store data when a first voltage is supplied to a gate of the first transistor and a second voltage is supplied to a second terminal of the first transistor,

wherein the storage element is configured to hold the data while a third voltage is supplied to the gate of the first transistor, and

wherein the storage element is configured to output the data while a fourth voltage is supplied to a first terminal of the second transistor and a fifth voltage is supplied to a second terminal of the capacitor.

21. The semiconductor device according to claim 15,

wherein the storage element comprises a capacitor,

wherein a first terminal of the first transistor is electrically connected to a first terminal of the capacitor,

wherein the storage element is configured to store data when a first voltage is supplied to a gate of the first transistor and a second voltage is supplied to a second terminal of the first transistor,

wherein the storage element is configured to hold the data while a third voltage is supplied to the gate of the first transistor, and

wherein the storage element is configured to output the data while a fourth voltage is supplied to the gate of the first transistor.