Methods and apparatus related to any-to-any connectivity within a data center

• US 8,730,954 B2
• Filed: 06/30/2009
• Issued: 05/20/2014
• Est. Priority Date: 09/11/2008
• Status: Active Grant

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Sindhu, Pradeep, Aybay, Gunes, Frailong, Jean-Marc, Venkatramani, Anjan, Vohra, Quaizar
• Primary Examiner(s): Ho, Chuong T
• Application Number:
  US12/495,337
• Publication Number:
  US 20100061394A1
• Time in Patent Office: 1,785 Days
• Field of Search: 370/388, 370/387, 370/386, 370/389, 370/391, 370/390
• US Class Current: 370/388
• CPC Class Codes: H04L 49/1515 Non-blocking multistage, e.g. Clos
• CPC Class Codes: H04L 49/1523 Parallel switch fabric planes
• CPC Class Codes: H04L 49/153 ATM switching fabrics having parallel switch planes
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 49/70 Virtual switches
• CPC Class Codes: H04Q 3/68 Grouping or interlacing selector groups or stages

Abstract

In one embodiment, an apparatus includes a switch core that defines a single logical entity and has a multi-stage switch fabric physically distributed across a plurality of chassis. The multi-stage switch fabric has a plurality of ingress ports and a plurality of egress ports. The switch core is configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports. The switch core is also configured to provide non-blocking connectivity at line rate between a first peripheral processing device disposed with a first chassis and a second peripheral processing device disposed within a second chassis.

Claims

1. An apparatus, comprising;

a switch core defining a single logical entity and having a multi-stage switch fabric physically distributed across a plurality of chassis, the multi-stage switch fabric having a plurality of ingress ports and a plurality of egress ports, the switch core configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports,

the switch core configured to provide non-blocking connectivity at line rate between a first peripheral processing device disposed with a first chassis and a second peripheral processing device disposed with a second chassis, the switch core configured to provide non-blocking connectivity at line rate between the second peripheral processing device and a third peripheral processing device,

the switch core configured to receive a first packet associated with the first peripheral processing device, the switch core configured to send sequentially a second packet to the second peripheral processing device and a third packet to the third peripheral processing device based on cells associated with the first packet, the multi-stage switch fabric configured to send the cells from ingress ports from the plurality of ingress ports to egress ports from the plurality of egress ports.

2. The apparatus of claim 1, wherein the plurality of peripheral processing devices includes at least one peripheral processing device coupled to the switch core via an Ethernet connection and at least one peripheral processing device coupled to the switch core via a non-Ethernet connection.

3. The apparatus of claim 1, wherein the plurality of peripheral processing devices includes at least one peripheral processing device using layer-3 routing and at least one peripheral processing device being a layer-4 through layer-7 device.

4. The apparatus of claim 1, wherein the plurality of peripheral processing devices includes at least one peripheral processing device with virtualized resources and at least one peripheral processing device without virtualized resources.

5. The apparatus of claim 1, wherein a number of the plurality of ingress ports and the plurality of egress ports is greater than 1000, each ingress port from the plurality of ingress ports and each egress port from the plurality of egress ports is configured to operate at a speed not less than 10 Gb/s.

6. The apparatus of claim 1, wherein:

the first peripheral processing device and the second peripheral processing device each is one of a storage node device, a computer node device, a service node device or a router.

7. The apparatus of claim 1, wherein:

the first peripheral processing device and the third peripheral processing device each is one of a storage node device, a computer node device, a service node device or a router; and

the second peripheral processing device is at least one of a firewall device, an intersection detection device or a load balance device.

8. An apparatus, comprising;

a switch core having a multi-stage switch fabric physically distributed across a plurality of chassis, the multi-stage switch fabric having a plurality of ingress ports and a plurality of egress ports, the switch core configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports,

the switch core configured to provide connectivity at line rate for each peripheral processing device from the plurality of peripheral processing devices to each remaining peripheral processing device from the plurality of peripheral processing devices such that each egress port from the plurality of egress ports is equitably accessible by each peripheral processing device from the plurality of peripheral processing devices via an ingress port from the plurality of ingress ports, a number of the plurality of ingress ports and the plurality of egress ports is greater than 1000, each ingress port from the plurality of ingress ports and each egress port from the plurality of egress ports is configured to operate at a speed not less than 10 Gb/s.

9. The apparatus of claim 8, wherein the plurality of peripheral processing devices includes at least one peripheral processing device coupled to the switch core via an Ethernet connection and at least one peripheral processing device coupled to the switch core via a non-Ethernet connection.

10. The apparatus of claim 8, wherein the plurality of peripheral processing devices includes at least one peripheral processing device using layer-3 routing and at least one peripheral processing device being a layer-4 through layer-7 device.

11. The apparatus of claim 8, wherein the plurality of peripheral processing devices includes at least one peripheral processing device with virtualized resources and at least one peripheral processing device without virtualized resources.

12. An apparatus, comprising:

a switch core defining a single logical entity and having a multi-stage switch fabric physically distributed across a plurality of chassis, the multi-stage switch fabric having a plurality of ingress ports and a plurality of egress ports, the plurality of ingress ports including a first ingress port and a second ingress port, the plurality of egress ports including a first egress port and a second egress port, the switch core configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports, the plurality of peripheral processing devices including a first peripheral device, a second peripheral device and a third peripheral device, the first ingress port associated with the first peripheral processing device, the second ingress port associated with the second peripheral processing device, the first egress port associated with the second peripheral processing device, the second egress port associated with the third peripheral processing device,

the switch core configured to receive a first packet associated with the first peripheral processing device, the switch core configured to send sequentially a second packet to the second peripheral processing device and a third packet to the third peripheral processing device based on cells associated with the first packet, the multi-stage switch fabric configured to send the cells from ingress ports from the plurality of ingress ports to egress ports from the plurality of egress ports, the multi-stage switch fabric configured to send a first subset of the cells from the first ingress port to the first egress port, the multi-stage switch fabric configured to send a second subset of the cells from the second ingress port to the second egress port.

13. The apparatus of claim 12, wherein:

the first peripheral processing device and the third peripheral processing device each is one of a storage node device, a computer node device, a service node device or a router; and

the second peripheral processing device being is at least one of a firewall device, an intrusion detection device or a load balancer device.

14. The apparatus of claim 12, wherein:

the switch core includes a plurality of edge devices coupled to the multi-stage switch fabric via the plurality of ingress ports and the plurality of egress ports, the plurality of edge devices coupled to the plurality of peripheral processing devices,

a first edge device from the plurality of edge devices configured to receive the first packet and define the first subset of cells based on the first packet,

a second edge device from the plurality of edge devices configured to receive the second packet and define the second subset of cells based on the first packet,

a third edge device from the plurality of edge devices configured to receive the third packet.

15. The apparatus of claim 12, wherein:

at least one of the first peripheral processing device, the second peripheral processing device and the third peripheral processing device is coupled to the switch core via an Ethernet connection,

at least one of the first peripheral processing device, the second peripheral processing device and the third peripheral processing device is coupled to the switch core via a non-Ethernet connection.

16. The apparatus of claim 12, wherein:

the first peripheral processing device and the third peripheral processing device each uses layer-3 routing, and

the second peripheral processing device is a layer-4 through layer-7 device.

17. The apparatus of claim 12, wherein:

at least one of the first peripheral processing device, the second peripheral processing device and the third peripheral processing device is configured with virtualized resources, and

at least one of the first peripheral processing device, the second peripheral processing device and the third peripheral processing device is configured without virtualized resources.

18. The apparatus of claim 12, wherein a number of the plurality of ingress ports and the plurality of egress ports is greater than 1000, each ingress port from the plurality of ingress ports and each egress port from the plurality of egress ports is configured to operate at a speed not less than 10 Gb/s.