System for performing finite input response (FIR) filtering in motion estimation

• US 8,731,071 B1
• Filed: 12/15/2005
• Issued: 05/20/2014
• Est. Priority Date: 12/15/2005
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Kimura, Scott A.
• Primary Examiner(s): SARPONG, AKWASI
• Application Number:
  US11/304,396
• Time in Patent Office: 3,078 Days
• Field of Search: 375/240.26, 345/690, 345/570, 345/531, 712/34, 712/36, 712/225, 712/795
• US Class Current: 375/240.29
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A system for performing finite input response filtering. The system includes an array of random access memories (RAMs) for storing at least one two-dimensional (2D) block of pixel data. The pixel data is stored such that one of each type of column or row from the 2D block of pixel data is stored per RAM. A control block provides address translation between the 2D block of pixel data and corresponding addresses in the array of RAMs. An input crossbar writes pixel data to the array of RAMs as directed by the control block. An output crossbar simultaneously reads pixel data from each of the array of RAMs and passes the data to an appropriate replicated data path, as directed by the control block. A single instruction multiple data path block includes a plurality of replicated data paths for simultaneously performing the FIR filtering, as directed by the control block.

Claims

1. A system for performing FIR filtering in motion estimation, comprising:

an array of a plurality of random access memories (RAMs) for storing at least one two-dimensional (2D) block of pixel data for a plurality of pixels, wherein said at least one block of pixel data is stored in said array of RAMs such that pixels, of each given column from said at least one 2D block of pixel data, are stored in different ones of said plurality of RAMs, or pixels, of each given row from said at least one 2D block of pixel data, are stored in different ones of said plurality of RAMs;

a control block for providing address translation between data arranged in said at least one 2D block of pixel data and corresponding addresses in said array of RAMs wherein pixels, of each given column from said at least one 2D block of pixel data, are stored in different ones of said plurality of RAMs, or pixels, of each given row from said at least one 2D block of pixel data, are stored in different ones of said plurality of RAMs;

an input crossbar for writing pixel data to said array of RAMs as directed by said control block;

an output crossbar for simultaneously reading pixel data from each one of said plurality of RAMs of said array and passing said data read from each of said plurality of RAMs to an appropriate replicated data path, as directed by said control block; and

a single instruction multiple data path (SIMD) block comprising a plurality of replicated data paths for simultaneously performing said FIR filtering on each of said replicated data paths, as directed by said control block.

2. The system of claim 1, further comprising:

a multiplexer for receiving pixel data from an external frame buffer storing previous frames and intermediate pixel data from said plurality of replicated data paths, and for arranging said received pixel data in a 128 bit word as input pixel data that is input to said input crossbar.

3. The system of claim 2, wherein said input crossbar further comprises:

a plurality of multiplexers for receiving said input pixel data and writing said input pixel data to said array of RAMs, wherein each of said plurality of multiplexers parse out appropriate pixel data for a corresponding RAM from said input of pixel data.

4. The system of claim 2, further comprising:

a plurality of output multiplexers each of which is associated with one RAM of said array of RAMs, wherein each of said plurality of output multiplexers selects an appropriate storage format in which said pixel data is stored in an associated RAM for use in said FIR filtering.

5. The system of claim 2, wherein said output crossbar further comprises:

a plurality of multiplexers for reading selected, pixel data stored in said array of RAMs.

6. The system of claim 1, wherein said output crossbar is capable of replicating edge pixels in said at least one 2D block of pixel data.

7. The system of claim 1, wherein said output crossbar is capable of simultaneously reading an even and odd row in said at least one 2D block of pixel data.

8. The system of claim 1, wherein said output crossbar is capable of simultaneously reading an even and odd column simultaneously.

9. The system of claim 1, wherein each of said array of RAMs comprises a plurality of addresses, wherein each of said plurality of addresses stores data associated with a corresponding and predefined pixel in screen coordinates from said at least one 2D block of pixel data.

10. The system of claim 1, wherein each of said replicated data paths in said SIMD block comprises:

an adder stage;

a multiplier state; and

an accumulator stage.

11. A system for performing FIR filtering in motion estimation, comprising:

an array of a plurality of random access memories (RAMs) for storing at least one two-dimensional (2D) block of pixel data for a plurality of pixels, wherein said at least one block of pixilated data is stored in said array of RAMs in a manner that multiple rows or columns of said at least one block, of pixilated data used for motion estimation can be read simultaneously by storing pixels, of each given column or each given row of said at least one 2D block of pixel data, in different ones of said plurality of RAMs, such that a set of pixels of the given column or the given row are each stored at different addresses within each respective one of the plurality of RAMs;

an input crossbar for receiving said at least one 2D block of pixel data and writing said at least one block of pixilated data to said array of RAMs, wherein pixels, of each given column or each given row of said at least one 2D block of pixel data, are stored in different ones of said plurality of RAMs, such that a set of pixels of the given column or the given row are each stored at different addresses within each respective one of the plurality of RAMs;

an output crossbar for simultaneously reading pixel data from each one of said plurality of RAMs of said array and passing said data read from each of said plurality of RAMs to an appropriate replicated data path, wherein one pixel, of each given column or each given row of said at least one 2D block of pixel data, is stored in different ones of said plurality of RAMs, such that a set of pixels of the given column or the given row are each stored at different addresses within each respective one of the plurality of RAMs;

a single instruction multiple data path (SIMD) block comprising a plurality of replicated data paths for simultaneously performing said FIR filtering on each of said replicated data paths, wherein each of said replicated data paths comprises an adder stage, a multiplier stage, and an accumulator stage; and

a control block for controlling data flow through said array of RAMs, said input cross bar, said output crossbar and said plurality of replicated data paths.

12. The system of claim 11, wherein each of said array of RAMs comprises a plurality of addresses, wherein each of said plurality of addresses stores data associated with a corresponding pixel in screen coordinates from said at least one block of pixel data.

13. The system of claim 11, further comprising:

a plurality of output multiplexers, each corresponding, to an associated RAM memory for selecting one of a plurality of storage formats in which said pixel data is stored in said associated RAM memory.

14. The system of claim 11, wherein said control block accesses said pixel data from external memory storing previous frames of data and accesses intermediate pixel data from said plurality of replicated data paths for input to said input crossbar.

15. The system of claim 11, wherein said control block, performs address translation so that said at least one 2D block of pixilated data is appropriately stored in said local buffer such that one of each type of column or row from said at least one 2D block of pixels is stored per RAM in said local buffer.

16. A system for performing FIR filtering in motion estimation comprising:

a plurality of storage traits for storing pixel data corresponding to at least;

one two-dimensional (2D) block of pixel data wherein each of a set of pixels of a given column;

or a given row of said at least one 2D block of pixel data is stored separately in different ones of said plurality of storage units in a manner that multiple rows or columns of said at least one block of pixel data can be read simultaneously from each one of said plurality of storage units;

a single instruction multiple data path (SIMD) block comprising a plurality of replicated data paths for simultaneously performing said FIR filtering of said at least one 2I) block of pixel data stored in said plurality of storage unit on each of said replicated data paths; and

control block for controlling data flow through said storage block and said SIMD block;

wherein said plurality of storage units further comprises;

an array of random access memories (RAMs) for storing said pixel data wherein said at least one block of pixilated data is stored in said array of RAMs such that one of each type of column or row from said at least one 2D block of pixels is stored in a different one of the plurality of RAMs of the array;

wherein said control block provides address translation between data received from said at least one 2D block of pixel data and corresponding addresses in said array of RAMs;

an input crossbar for writing pixel data to said array of RAMs as directed by said control block; and

an output crossbar for simultaneously reading pixel data from each one of said plurality of RAMs of said array and passing said data read from each of said plurality of RAMs m an appropriate replicated data path, as directed by said control block.

17. The system of claim 16, wherein said output crossbar is capable of replicating edge pixels, of reading, an even and odd row simultaneously, and of reading an even and odd column simultaneously.

18. The system of claim 16, wherein said output crossbar is capable of reading either rows or columns of said at least one 20 block of pixel data.

19. The system of claim 16, wherein each of said replicated data paths in said SIMD block comprises;

an adder stage;

a multiplier stage; and

an accumulator stage.