Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering

• US 8,732,225 B1
• Filed: 10/11/2013
• Issued: 05/20/2014
• Est. Priority Date: 03/03/2010
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Yi, Hyun, Demirsoy, Suleyman
• Primary Examiner(s): SUN, SCOTT C
• Application Number:
  US14/051,759
• Time in Patent Office: 221 Days
• Field of Search: None
• US Class Current: 708/490
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use (e.g., in multiple instances of the DSP block circuitry on the IC) for implementing finite-impulse-response (“FIR”) digital filters in systolic form. Each DSP block may include (1) first and second multiplier circuitry and (2) adder circuitry for adding (a) outputs of the multipliers and (b) signals chained in from a first other instance of the DSP block circuitry. Systolic delay circuitry is provided for either the outputs of the first multiplier (upstream from the adder) or at least one of the sets of inputs to the first multiplier. Additional systolic delay circuitry is provided for outputs of the adder, which are chained out to a second other instance of the DSP block circuitry.

Claims

1. Digital signal processing (“

DSP”

) block circuitry comprising;

first multiplier circuitry for producing a first output signal indicative of a first multiplication product of a multiplicand signal and a multiplier signal;

first systolic delay circuitry for delaying at least one of (1) the multiplicand signal and (2) the multiplier signal by at least one systolic delay time interval;

second multiplier circuitry for producing a second output signal indicative of a second multiplication product;

adder circuitry for adding the first and second output signals and a third signal indicative of a data value received from a first other instance of said DSP block circuitry;

output register circuitry for registering an output signal of the adder circuitry; and

second systolic delay circuitry for delaying output of the output register circuitry by at least one of the systolic delay time interval.

2. The DSP block circuitry defined in claim 1 further comprising:

circuitry for applying output of the second systolic delay circuitry to a second other instance of said DSP block circuitry as said third signal of said second other instance.

3. The DSP block circuitry defined in claim 1 wherein the first systolic delay circuitry delays both the multiplicand signal and the multiplier signal by the systolic delay time interval.

4. The DSP block circuitry defined in claim 1 in combination with:

circuitry for applying a succession of input signal samples to the first systolic delay circuitry as the multiplicand signals;

circuitry for delaying each of the input signal samples by a time period equal to the sum of (1) duration of each of the input signal samples in the succession, and (2) the systolic delay time interval; and

circuitry for applying output of the circuitry for delaying to the second multiplier circuitry.

5. The DSP block circuitry defined in claim 4 wherein the systolic delay time interval is equal to the duration of each of the input signal samples in the succession.

6. The DSP block circuitry defined in claim 1 further comprising:

circuitry for controllably allowing signals to bypass the first systolic delay circuitry.

7. The DSP block circuitry defined in claim 1 further comprising:

circuitry for controllably allowing signals to bypass the second systolic delay circuitry.

8. The DSP block circuitry defined in claim 1 wherein the adder circuitry comprises:

means for additively combining the first and second output signals to produce an intermediate signal; and

means for additively combining the intermediate signal and the third signal.

9. The DSP block circuitry defined in claim 1 further comprising:

third multiplier circuitry for producing a fourth output signal indicative of a third multiplication product of a third multiplicand signal and a third multiplier signal; and

third systolic delay circuitry for delaying at least one of (1) the third multiplicand signal and (2) the third multiplier signal by a second systolic delay time interval which is a fraction of the systolic delay time interval; and

wherein the adder circuitry additionally adds the fourth output signal.

10. The DSP block circuitry defined in claim 4 wherein the circuitry for delaying each of the input signal samples by a time period equal to the sum of (1) duration of each of the input signal samples in the succession, and (2) the systolic delay time interval is part of the DSP block circuitry.

11. The DSP block circuitry defined in claim 1, further comprising:

third systolic delay circuitry for delaying the first output signal by three multiples of the systolic delay time interval;

fourth systolic delay circuitry for delaying the second output signal by two multiples of the systolic delay time interval;

third multiplier circuitry for producing a fourth output signal indicative of a third multiplication product;

fifth systolic delay circuitry for delaying the fourth output signal by the systolic delay time interval; and

fourth multiplier circuitry for producing a fifth output signal indicative of a fourth multiplication product;

wherein;

the adder circuitry further adds (1) outputs of the third, fourth, and fifth systolic delay circuitries, and (2) the fifth output signal with the first and second output signals and the third signal indicative of the data value received from the first other instance of said DSP block circuitry.

12. The DSP block circuitry defined in claim 11 wherein:

the second systolic delay circuitry delays outputs of the output register circuitry by three multiples of the systolic delay time interval.

13. The DSP block circuitry defined in claim 1, wherein:

the first systolic delay circuitry delays at least one of (1) the first multiplicand signal and (2) the first multiplier signal by three multiples of the systolic delay time interval; and

the second multiplier circuitry produces the second output signal indicative of the second multiplication product from inputs of a second multiplicand signal and a second multiplier signal;

said DSP block circuitry further comprising;

third systolic delay circuitry for delaying at least one of (1) the second multiplicand signal and (2) the second multiplier signal by two multiples of the systolic delay time interval;

third multiplier circuitry for producing a third output signal indicative of a third multiplication product of a third multiplicand signal and a third multiplier signal;

fourth systolic delay circuitry for delaying at least one of (1) the third multiplicand signal and (2) the third multiplier signal by the systolic delay time interval; and

fourth multiplier circuitry for producing a fourth output signal indicative of a fourth multiplication product;

wherein;

the adder circuitry further adds the third and fourth output signals with the first and second output signals and the third signal indicative of the data value received from the first other instance of said DSP block circuitry.

14. The DSP block circuitry defined in claim 13 wherein:

the second systolic delay circuitry delays the outputs of the output register circuitry by three multiples of the systolic delay time interval.

15. Digital signal processing (“

DSP”

) block circuitry comprising;

first multiplier means for producing a first output signal indicative of a first multiplication product of a multiplicand signal and a multiplier signal;

first systolic delay means for delaying at least one of (1) the multiplicand signal and (2) the multiplier signal by at least one systolic delay time interval;

second multiplier means for producing a second output signal indicative of a second multiplication product;

adder means for adding the first and second output signals and a third signal indicative of a data value received from a first other instance of said DSP block circuitry;

output register means for registering an output signal of the adder means; and

second systolic delay means for delaying output of the output register means by at least one of the systolic delay time interval.

16. The DSP block circuitry defined in claim 15 further comprising:

means for applying output of the second systolic delay means to a second other instance of said DSP block circuitry as said third signal of said second other instance.

17. The DSP block circuitry defined in claim 15 wherein the first systolic delay means delays both the multiplicand signal and the multiplier signal by the systolic delay time interval.

18. The DSP block circuitry defined in claim 15 in combination with:

means for applying a succession of input signal samples to the first systolic delay circuitry as the multiplicand signals;

means for delaying each of the input signal samples by a time period equal to the sum of (1) duration of each of the input signal samples in the succession, and (2) the systolic delay time interval; and

means for applying output of the circuitry for delaying to the second multiplier means.

19. The DSP block circuitry defined in claim 15 wherein the adder means comprises:

means for additively combining the first and second output signals to produce an intermediate signal; and

means for additively combining the intermediate signal and the third signal.

20. The DSP block circuitry defined in claim 15 further comprising:

third multiplier means for producing a fourth output signal indicative of a third multiplication product of a third multiplicand signal and a third multiplier signal; and

third systolic delay means for delaying at least one of (1) the third multiplicand signal and (2) the third multiplier signal by a second systolic delay time interval which is a fraction of the systolic delay time interval; and

wherein the adder means additionally adds the fourth output signal.

21. Digital signal processing (“

DSP”

) block circuitry comprising;

first multiplier circuitry for producing a first plurality of parallel output signals indicative of a first multiplication product of a plurality of parallel multiplicand signals and a plurality of parallel multiplier signals;

first systolic delay circuitry for delaying at least one of (1) the plurality of parallel multiplicand signals and (2) the plurality of parallel multiplier signals by at least one systolic delay time interval;

second multiplier circuitry for producing a second plurality of parallel output signals indicative of a second multiplication product;

adder circuitry for adding the first and second pluralities of output signals and a third plurality of parallel signals indicative of a data value received from a first other instance of said DSP block circuitry; and

output register circuitry for registering output signals of the adder circuitry.

22. The DSP block circuitry defined in claim 21 further comprising:

circuitry for applying outputs of the DSP block circuitry to a second other instance of said DSP block circuitry as said third plurality of parallel signals of said second other instance.

23. The DSP block circuitry defined in claim 21 wherein the first systolic delay circuitry delays both the plurality of parallel multiplicand signals and the plurality of parallel multiplier signals by the systolic delay time interval.

24. The DSP block circuitry defined in claim 21 in combination with:

circuitry for applying a succession of input signal samples to the first systolic delay circuitry as the multiplicand signals;

circuitry for delaying each of the input signal samples by a time period equal to the sum of (1) duration of each of the input signal samples in the succession, and (2) the systolic delay time interval; and

circuitry for applying outputs of the circuitry for delaying to the second multiplier circuitry.

25. The DSP block circuitry defined in claim 24 wherein the systolic delay time interval is equal to the duration of each of the input signal samples in the succession.

26. The DSP block circuitry defined in claim 21 further comprising:

circuitry for controllably allowing signals to bypass the first systolic delay circuitry.

27. The DSP block circuitry defined in claim 21 wherein the adder circuitry comprises:

means for additively combining the first and second pluralities of output signals to produce a plurality of parallel intermediate signals; and

means for additively combining the plurality of parallel intermediate signals and the third plurality of parallel signals.

28. The DSP block circuitry defined in claim 24 wherein the circuitry for delaying each of the input signal samples by a time period equal to the sum of (1) duration of each of the input signal samples in the succession, and (2) the systolic delay time interval is part of the DSP block circuitry.