Dynamic allocation of buffers for direct memory access
First Claim
Patent Images
1. A device comprising:
- unified DMA (‘
Direct Memory Access’
) storage;
a processor operatively coupled to the unified DMA storage and a main memory; and
a plurality of DMA (‘
Direct Memory Access’
) engines, wherein the plurality of DMA engines are configured to access the unified DMA storage and provide DMA transmissions between the main memory and a corresponding component; and
wherein the processor is configured to;
determine a size of a corresponding DMA buffer to be allocated for each DMA engine;
allocate, for each DMA engine, the corresponding DMA buffer of the determined size in the unified DMA memory; and
execute DMA transmissions using the DMA engines and the corresponding DMA buffers.
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Abstract
A device includes a processor, unified DMA (‘Direct Memory Access’) storage, and a number of DMA engines. The processor may be operatively coupled to the unified DMA storage and a main memory. The DMA engines may be configured to access the unified DMA storage and provide DMA transmissions between the main memory and a corresponding component. The processor may be configured to: determine a size of a corresponding DMA buffer to be allocated for each DMA engine; allocate, for each DMA engine, the corresponding DMA buffer of the determined size in the unified DMA storage; and execute DMA transmission using the DMA engines and the corresponding DMA buffers.
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Citations
25 Claims
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1. A device comprising:
-
unified DMA (‘
Direct Memory Access’
) storage;a processor operatively coupled to the unified DMA storage and a main memory; and a plurality of DMA (‘
Direct Memory Access’
) engines, wherein the plurality of DMA engines are configured to access the unified DMA storage and provide DMA transmissions between the main memory and a corresponding component; andwherein the processor is configured to; determine a size of a corresponding DMA buffer to be allocated for each DMA engine; allocate, for each DMA engine, the corresponding DMA buffer of the determined size in the unified DMA memory; and execute DMA transmissions using the DMA engines and the corresponding DMA buffers. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of dynamically administering DMA (‘
- Direct Memory Access’
) buffers for a plurality of DMA engines, wherein each DMA engine is configured to provide DMA transmissions between a main memory and a corresponding component, the method comprising;determining, by the processor, a size of a corresponding DMA buffer to be allocated for each DMA engine; allocating, by the processor for each DMA engine, the corresponding DMA buffer of the determined size in unified DMA storage accessible by the DMA engines; and executing DMA transmissions using the DMA engines and corresponding DMA buffers. - View Dependent Claims (9, 10, 11, 12)
- Direct Memory Access’
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13. A processor for dynamically administering DMA (‘
- Direct Memory Access’
) buffers for a plurality of DMA engines, wherein each DMA engine is configured to provide DMA transmission between a main memory and a corresponding component, wherein the processor is configured to;determine a size of a corresponding DMA buffer to be allocated for each DMA engine; allocate, for each DMA engine, the corresponding DMA buffer of the determined size in unified DMA storage accessible by the DMA engines; and execute DMA transmissions using the DMA engines and the corresponding DMA buffers. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
- Direct Memory Access’
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21. A computer readable storage medium including computer program instructions for dynamically administering DMA (‘
- Direct Memory Access’
) buffers for a plurality of DMA engines, wherein each DMA engine is configured to provide DMA transmissions between a main memory and a corresponding component and the computer program instructions are executable by the processor to;determine a size of a corresponding DMA buffer to be allocated for each DMA engine; allocate, for each DMA engine, the corresponding DMA buffer of the determined size in unified DMA storage accessible by the DMA engines; and execute DMA transmissions using the DMA engines and the corresponding DMA buffers. - View Dependent Claims (22, 23, 24, 25)
- Direct Memory Access’
Specification