Memory system and control method thereof

• US 8,732,553 B2
• Filed: 09/21/2011
• Issued: 05/20/2014
• Est. Priority Date: 12/27/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nagadomi, Yasushi, Takashima, Daisaburo
• Primary Examiner(s): LAMARRE, GUY J
• Application Number:
  US13/238,685
• Publication Number:
  US 20120166906A1
• Time in Patent Office: 972 Days
• Field of Search: 714/768, 714/755, 714/786, 714/777, 714/782
• US Class Current: 714/768
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2927 Decoding strategies
• CPC Class Codes: H03M 13/2945 using at least three error correction codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/6561 Parallelized implementations

Abstract

The embodiments include an error correction processing unit and an error correction history recording unit. The error correction processing unit performs an error correction process based on data read from a non-volatile semiconductor memory and a second-step error correction code corresponding to the data. The error correction history recording unit records error correction history indicating whether first error correction is successful through the first error correction process, in association with unit data. When error correction history of target unit data to be read indicates that correction is not successful, the second error correction process is executed without executing the first error correction process.

Claims

1. A memory system comprising:

a non-volatile semiconductor memory;

an encoder that performs a first encoding process using unit data to generate first parity, and a second encoding process using the unit data to generate second parity;

a memory interface that writes, into the non-volatile semiconductor memory, the unit data, the first parity, and the second parity;

an error correction processing unit that performs a first error correction process based on the unit data read from the non-volatile semiconductor memory and the first parity corresponding to the unit data, and a second error correction process based on the unit data read from the non-volatile semiconductor memory and the second parity corresponding to the unit data;

an error correction history recording unit which records error correction history indicating whether the first error correction process is not successful by the error correction processing unit, in association with each unit data; and

an error correction processing control unit that controls the error correction processing unit to perform the first error correction process for the unit data read from the non-volatile semiconductor memory when the error correction history corresponding to the unit data is not recorded or indicates that the first error correction process was successful, controls the error correction processing unit to perform the second error correction process for the unit data when the first error correction process is not successful, and controls the error correction processing unit to perform the second error correction process for the unit data read from the non-volatile semiconductor memory without performing the first error correction process for the unit data when the error correction history corresponding to the unit data indicates that the first error correction process was not successful.

2. The memory system according to claim 1, wherein the error correction history is stored in the non-volatile semiconductor memory.

3. The memory system according to claim 1, wherein the error correction history includes a number of correction bits for the error correction process using the first parity.

4. The memory system according to claim 3, wherein the error correction processing control unit performs the first error correction process and parallelly starts to perform the second error correction process, when the number of correction bits corresponding to the unit data to be read is equal to or greater than a first threshold value.

5. The memory system according to claim 4, wherein the error correction processing control unit performs the first error correction process and parallelly starts to perform the second error correction process, when the number of correction bits corresponding to the unit data to be read is equal to or greater than the first threshold value, and when a number of times corresponding to the unit data is read is equal to or greater than a second threshold value.

6. The memory system according to claim 1, further comprising a semiconductor memory configured to temporarily record the error correction history.

7. The memory system according to claim 6, wherein the semiconductor memory is a non-volatile memory.

8. The memory system according to claim 6, wherein

the semiconductor memory is a volatile memory, and

the error correction history recorded in the semiconductor memory is written into the non-volatile semiconductor memory, when power is OFF, and the error correction history is read from the non-volatile semiconductor memory and written into the semiconductor memory, when power is ON.

9. The memory system according to claim 1, wherein when the unit data recorded in the non-volatile semiconductor memory is updated, the error correction history corresponding to the unit data is initialized.

10. The memory system according to claim 1, wherein the first parity is generated by error correction code and includes a hamming code or a BCH code for enabling correction for a small number of bits, and the second parity is generated by error correction code and includes a BCH code for enabling correction for a large number of bits or an LDPC code.

11. A control method for a memory system that includes a non-volatile semiconductor memory, comprising:

performing a first encoding process using unit data to generate first parity, and a second encoding process using the unit data to generate second parity;

writing, into the non-volatile semiconductor memory, the unit data, the first parity, and the second parity;

performing a first error correction process based on the unit data read from the non-volatile semiconductor memory and the first parity corresponding to the unit data, and a second error correction process based on the unit data read from the non-volatile semiconductor memory and the second parity corresponding to the unit data;

recording error correction history indicating whether the first error correction process is successful, in association with each unit data;

controlling to perform the first error correction process for the unit data read from the non-volatile semiconductor memory when the error correction history corresponding to the unit data is not recorded or indicates that the first error correction process was successful;

controlling to perform the second error correction process for the unit data when the first error correction process is not successful; and

controlling to perform the second error correction process for the unit data read from the non-volatile semiconductor memory without performing the first error correction process for the unit data when the error correction history corresponding to the unit data indicates that the first error correction process was not successful.

12. The control method for a memory system according to claim 11, further comprising recording the error correction history into the non-volatile semiconductor memory.

13. The control method for a memory system according to claim 11, wherein the error correction history includes a number of correction bits for the error correction process using the first parity.

14. The control method for a memory system according to claim 13, further comprising:

performing the first error correction process, and also controlling parallelly to start the second error correction process, when the number of correction bits corresponding to the unit data to be read is equal to or greater than a first threshold value.

15. The control method for a memory system according to claim 14, further comprising performing the first error correction process, and controlling to parallelly perform the second error correction process, when the number of correction bits corresponding to the unit data to be read is equal to or greater than the first threshold value, and when a number of times corresponding to the unit data is read is equal to or greater than a second threshold value.

16. The control method for a memory system according to claim 11, further comprising temporarily recording the error correction history in a semiconductor memory.

17. The control method for a memory system according to claim 16, wherein the semiconductor memory is a non-volatile memory.

18. The control method for a memory system according to claim 16, wherein

the semiconductor memory is a volatile memory, and

the error correction history recorded in the semiconductor memory is written into the non-volatile semiconductor memory, when power is OFF, and the error correction history is read from the non-volatile semiconductor memory and written into the semiconductor memory, when power is ON.

19. The control method for a memory system according to claim 11, wherein when the unit data recorded in the non-volatile semiconductor memory is updated, the error correction history corresponding to the unit data is initialized.

20. The control method for a memory system according to claim 11, wherein the first parity is generated by error correction code and includes a hamming code or a BCH code for enabling correction for a small number of bits, and the second parity is generated by error correction code and includes a BCH code for enabling correction for a large number of bits or an LDPC code.