Method and apparatus for parallel processing in a gigabit LDPC decoder

• US 8,732,565 B2
• Filed: 06/13/2011
• Issued: 05/20/2014
• Est. Priority Date: 06/14/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Pisek, Eran, Abu-Surra, Shadi
• Primary Examiner(s): MCMAHON, DANIEL F
• Application Number:
  US13/159,091
• Publication Number:
  US 20110307760A1
• Time in Patent Office: 1,072 Days
• Field of Search: None
• US Class Current: 714/804
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/114 Shuffled, staggered, layered or turbo decoding schedules
• CPC Class Codes: H03M 13/116 Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence

Abstract

A receiver for use in a wireless communications network capable of decoding encoded transmissions. The receiver comprises receive path circuitry for receiving and downconverting an incoming radio frequency (RF) signal to produce an encoded received signal; and a low-density parity check (LDPC) decoder associated with the receive path circuitry for decoding the encoded received signal. The LDPC decoder further comprises a memory for storing a parity check H matrix comprising R rows and C columns, where each element of the parity check H matrix comprises one of a shift value or a −1 value; and a plurality of processing elements for performing LDPC layered decoding, wherein at least one processing element is operable to process in the same cycle a first row and a second row of the parity check H matrix.

Claims

1. For use in a wireless communications device, a receiver comprising:

receive path circuitry configured to receive and down-convert an incoming radio frequency (RF) signal to produce an encoded received signal; and

a low-density parity check (LDPC) decoder associated with the receive path circuitry, the LDPC decoder configured to decode the encoded received signal, the LDPC decoder comprising;

a memory configured to store a parity check H matrix comprising R rows and C columns, where each element of the parity check H matrix comprises one of a shift value or a non-use value indicating not to be used; and

a plurality of processing elements configured to perform LDPC layered decoding, wherein at least one processing element is configured to process in a same cycle a first row and a second row of the parity check H matrix.

2. The receiver as set forth in claim 1, wherein elements of the first row and elements of the second row are mutually exclusive.

3. The receiver as set forth in claim 1, wherein for each element of the first row having a shift value, a corresponding element in a same column in the second row has a −

1 value.

4. The receiver as set forth in claim 3, wherein for each element of the first row having a −

1 value, a corresponding element in the same column in the second row has a shift value.

5. The receiver as set forth in claim 1, wherein the parity check H matrix is associated with a rate 1/2 code.

6. The receiver as set forth in claim 1, wherein the parity check H matrix is associated with a rate 5/8 code.

7. For use in a wireless communications device, a method of decoding comprising:

in a receiving device, receiving and down-converting an incoming radio frequency (RF) signal to produce an encoded received signal; and

decoding the encoded received signal in a low-density parity check (LDPC) decoder, the LDPC decoder comprising a memory configured to store a parity cheek H matrix comprising R rows and C columns, where each element of the parity check H matrix comprises one of a shift value or a non-use value indicating not to be used; and

in a processing element of the decoder configured to perform LDPC layered decoding, processing in a same cycle a first row and a second row of the parity check H matrix.

8. The method as set forth in claim 7, wherein elements of the first row and elements of the second row are mutually exclusive.

9. The method as set forth in claim 7, wherein for each element of the first row having a shift value, a corresponding element in a same column in the second row has a −

1 value.

10. The method as set forth in claim 9, wherein for each element of the first row having a −

1 value, a corresponding element in the same column in the second row has a shift value.

11. The method as set forth in claim 7, wherein the parity check H matrix is associated with a rate 1/2 code.

12. The method as set forth in claim 7, wherein the parity check H matrix is associated with a rate 5/8 code.

13. For use in a wireless network, a mobile station capable of communicating with at least one base station of the wireless network, the mobile station comprising:

receive path circuitry configured to receive and down-convert an incoming radio frequency (RF) signal transmitted by the at least one base station to produce an encoded received signal; and

a low-density parity check (LDPC) decoder associated with the receive path circuitry, the LDPC decoder configured to decode the encoded received signal, the LDPC decoder comprising;

a memory configured to store a parity check H matrix comprising R rows and C columns, where each element of the parity check H matrix comprises one of a shift value or a non-use value; and

a plurality of processing elements configured to perform LDPC layered decoding, wherein at least one processing element is configured to process in a same cycle a first row and a second row of the parity check H matrix.

14. The mobile station as set forth in claim 13, wherein elements of the first row and elements of the second row are mutually exclusive.

15. The mobile station as set forth in claim 13, wherein for each element of the first row having a shift value, a corresponding element in a same column in the second row has a −

1 value.

16. The mobile station as set forth in claim 15, wherein for each element of the first row having a −

1 value, a corresponding element in the same column in the second row has a shift value.

17. The mobile station as set forth in claim 13, wherein the parity check H matrix is associated with a rate 1/2 code.

18. The mobile station as set forth in claim 13, wherein the parity check H matrix is associated with a rate 5/8 code.

19. The mobile station as set forth in claim 13, wherein the receive path comprises an orthogonal frequency division multiple access (OFDMA) receive path.

20. The mobile station as set forth in claim 13, wherein the mobile station operates according to the 1.0 WiGig specification.