Method and apparatus for versatile controllability and observability in prototype system

• US 8,732,650 B2
• Filed: 08/29/2012
• Issued: 05/20/2014
• Est. Priority Date: 02/12/2010
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated, Synopsys Taiwan Co., Ltd. (Synopsys Incorporated)
• Inventors: Chang, Yingtsai, Shei, Sweyyan, Chiu, Hung Chun, Mao, Hwa, Wang, Ming Yang, Hsu, Yuchin
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US13/597,997
• Publication Number:
  US 20130035925A1
• Time in Patent Office: 629 Days
• Field of Search: 716/106, 716/108, 716/111, 716/116, 716/117, 716/136
• US Class Current: 716/136
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.

Claims

1. A system for emulating a circuit design, the system comprising:

a custom prototype board comprising at least one field programmable gate array (“

FPGA”

) for emulating the circuit design, the at least one FPGA of the custom prototype board being capable of emulating at least a portion of the circuit design, the at least one FPGA also being capable of being configured to include a verification module that provides timing and control information to the at least a portion of the circuit design and probing signals associated with the at least a portion of the circuit design, the custom prototype board being described by at least one board description file;

a host workstation capable of providing image data representative of the at least a portion of the circuit design being emulated and of the verification module, the image data being based at least in part on the at least one board description file and to be downloaded to the at least one FPGA on the custom prototype board; and

an emulation interface coupled between the host workstation and the custom prototype board, the emulation interface being capable of providing timing and control information to at least the verification module, the emulation interface comprising a controller and a memory device, wherein the controller is capable of being configured to receive and process signal values associated with the probed signals to store the processed signal values in the memory device.

2. The system of claim 1, wherein the verification module is a module defined by VHDL, HDL, Verilog, or netlist descriptions, the verification module being merged with a partitioned portion of the circuit design to form the image data downloaded to the at least one FPGA.

3. The system of claim 1, wherein a runtime database identifies at least the signals to be probed by the verification module and a frequency of monitoring those signals to be probed.

4. The system of claim 1, wherein the image data is created by a place and route software associated with the at least one FPGA.

5. The system of claim 1, wherein at least a first portion of the custom prototype board supplies the probed signals in an encoded form to the controller, and at least a second portion of the custom prototype board supplies at least one probe sampling system clock signal and at least one reference clock signal to the controller.

6. The system of claim 1, wherein the at least one board description file comprises at least one of Verilog description and VHDL description.

7. An emulation interface comprising:

a controller coupled between a host workstation and a custom prototype board, the controller being capable of receiving, after configuration, signal values associated with probed signals from a verification module of the custom prototype board, the custom prototype board being external to the emulation interface and comprising at least one field programmable gate array (“

FPGA”

) being capable of being configured to include the verification module, the probed signal values being associated with at least a portion of a circuit design being emulated by the custom prototype board; and

a memory device coupled with the controller to store information associated with the probed signal values, wherein the custom prototype board being described by at least one board description file, and the controller being capable of being configured to provide timing and control information to at least the verification module.

8. The emulation interface of claim 7, wherein at least a first portion of the custom prototype board supplies the probed signals in an encoded form to the controller, and at least a second portion of the custom prototype board supplies at least one probe sampling system clock signal and at least one reference clock signal to the controller.

9. A method for emulating a circuit design, the method comprising:

receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board, the custom prototype board being external to the emulation interface and comprising at least one field programmable gate array (“

FPGA”

), the at least one FPGA of the custom prototype board being capable of being configured to emulate at least a portion of the circuit design and being capable of being configured to provide the verification module, the custom prototype board being described by at least one board description file;

processing, by the emulation interface, the probed signal values, the probed signal values being associated with at least a portion of the circuit design being emulated, the emulation interface being coupled between a host workstation and the custom prototype board, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, the emulation interface comprising a controller and a memory device, the controller being capable of being configured to receive the probed signal values;

storing, by the emulation interface, processed information from processing the probed signal values by the controller; and

transmitting, by the emulation interface, the processed information to the host workstation.

10. The method of claim 9, wherein the verification module is merged with a partitioned portion of the circuit design to form an image data to be downloaded to the at least one FPGA, the verification module being defined by VHDL, HDL, Verilog, or netlist descriptions.

11. The method of claim 10, wherein the image data is created by a place and route software associated with the at least one FPGA.

12. The method of claim 9, wherein the receiving the signal values associated with probed signals is facilitated by a runtime database that identifies at least the signals to be probed and a frequency of monitoring those signals to be probed.

13. The method of claim 9, wherein the at least one board description file comprises VHDL, HDL, Verilog, or netlist descriptions.

14. The method of claim 9, further comprising, before receiving the signal values associated with the probed signals, configuring the custom prototype board to provide the verification module.

15. A non-transitory computer-readable medium comprising instructions that, when executed, causes a computer to perform a method for emulating a circuit design, the method comprising:

receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board, the custom prototype board being external to the emulation interface and comprising at least one field programmable gate array (“

FPGA”

), the at least one FPGA of the custom prototype board being capable of being configured to emulate at least a portion of the circuit design and being capable of being configured to include the verification module, the custom prototype board being described by at least one board description file;

processing, by the emulation interface, the probed signal values, the probed signal values being associated with at least a portion of the circuit design being emulated, the emulation interface being coupled between a host workstation and the custom prototype board, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, the emulation interface comprising a controller and a memory device, the controller being capable of being configured to receive the probed signal values;

storing, by the emulation interface, processed information from processing the probed signal values by the controller; and

transmitting, by the emulation interface, the processed information to the host workstation.

16. The computer-readable medium of claim 15, wherein the verification module is merged with a partitioned portion of the circuit design to form an image data to be downloaded to the at least one FPGA, the verification module being defined by VHDL, HDL, Verilog, or netlist descriptions.

17. The computer-readable medium of claim 16, wherein the image data is created by a place and route software associated with the at least one FPGA.

18. The computer-readable medium of claim 15, wherein the receiving the signal values associated with probed signals is facilitated by a runtime database that identifies at least the signals to be probed and a frequency of monitoring those signals to be probed.

19. The computer-readable medium of claim 15, wherein the at least one board description file comprises VHDL, HDL, Verilog, or netlist descriptions.

20. The computer-readable medium of claim 15, the method further comprising, before receiving the signal values associated with the probed signals, configuring the custom prototype board to provide the verification module.

21. A system for emulating a circuit design, the system comprising:

a custom prototype board comprising at least one field programmable gate array (“

FPGA”

) for emulating the circuit design, the at least one FPGA of the custom prototype board being configured to emulate at least a portion of the circuit design, the at least one FPGA also being configured to include a verification module that provides timing and control information to the at least a portion of the circuit design and probing signals associated with the at least a portion of the circuit design, the custom prototype board being described by at least one board description file;

a host workstation configured to provide image data representative of the at least a portion of the circuit design being emulated and of the verification module, the image data being based at least in part on the at least one board description file and to be downloaded to the at least one FPGA on the custom prototype board; and

an emulation interface coupled between the host workstation and the custom prototype board, the emulation interface being configured to provide timing and control information to at least the verification module, the emulation interface comprising a controller and a memory device, wherein the controller being configured to receive and process signal values associated with the probed signals to store the processed signal values in the memory device.

22. An emulation interface comprising:

a controller coupled between a host workstation and a custom prototype board, the controller being configured to receive, after configuration, signal values associated with probed signals from a verification module of the custom prototype board, the custom prototype board being external to the emulation interface and comprising at least one field programmable gate array (“

FPGA”

) being configured to include the verification module, the probed signal values being associated with at least a portion of a circuit design being emulated by the custom prototype board; and

a memory device coupled with the controller to store information associated with the probed signal values, wherein the custom prototype board being described by at least one board description file, and the controller being configured to provide timing and control information to at least the verification module.

23. A method for emulating a circuit design, the method comprising:

receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board, the custom prototype board being external to the emulation interface and comprising at least one field programmable gate array (“

FPGA”

), the at least one FPGA of the custom prototype board being configured to emulate at least a portion of the circuit design and being configured to include the verification module, the custom prototype board being described by at least one board description file;

processing, by the emulation interface, the probed signal values, the probed signal values being associated with at least a portion of the circuit design being emulated, the emulation interface being coupled between a host workstation and the custom prototype board, the emulation interface being configured to provide timing and control information to at least the verification module, the emulation interface comprising a controller and a memory device, the controller being configured to receive the probed signal values;

storing, by the emulation interface, processed information from processing the probed signal values by the controller; and

transmitting, by the emulation interface, the processed information to the host workstation.

24. A non-transitory computer-readable medium comprising instructions that, when executed, causes a computer to perform a method for emulating a circuit design, the method comprising:

receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board, the custom prototype board being external to the emulation interface and comprising at least one field programmable gate array (“

FPGA”

), the at least one FPGA of the custom prototype board being configured to emulate at least a portion of the circuit design and being configured to include the verification module, the custom prototype board being described by at least one board description file;

processing, by the emulation interface, the probed signal values, the probed signal values being associated with at least a portion of the circuit design being emulated, the emulation interface being coupled between a host workstation and the custom prototype board, the emulation interface being configured to provide timing and control information to at least the verification module, the emulation interface comprising a controller and a memory device, the controller being configured to receive the probed signal values;

storing, by the emulation interface, processed information from processing the probed signal values by the controller; and

transmitting, by the emulation interface, the processed information to the host workstation.