Integrated set-top box

• US 8,732,788 B2
• Filed: 05/20/2005
• Issued: 05/20/2014
• Est. Priority Date: 05/21/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: McMullin, Donald G., Burns, Lawrence M., Dauphinee, Leonard, Gomez, Ramon A., Tan, Loke
• Primary Examiner(s): Rabovianksi, Jivka
• Application Number:
  US11/133,237
• Publication Number:
  US 20060026661A1
• Time in Patent Office: 3,287 Days
• Field of Search: 725/126, 725/127, 725/151, 725/131, 725/139, 725/134
• US Class Current: 725/151
• CPC Class Codes: H04N 21/40 Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
• CPC Class Codes: H04N 21/6168 involving cable transmission, e.g. using a cable modem
• CPC Class Codes: H04N 7/17309 Transmission or handling of upstream communications

Abstract

The present invention is an integrated set-top box. In one embodiment, the up-stream path and the down-stream path are integrated on a common semiconductor substrate. The down-stream path can include a TV tuner and a digital receiver portion that is integrated on the common semiconductor substrate with a power amplifier of the up-stream path. In another embodiment, the TV tuner is implemented on a first semiconductor substrate and the digital receiver portion and the power amplifier are configured on a second semiconductor substrate. However, the two substrates are mounted on a common carrier so that the set-top box appears to be a single chip configuration to the user.

Claims

1. An integrated set-top box, comprising:

a common semiconductor substrate;

a down-stream path disposed on said common semiconductor substrate configured to down-convert a radio frequency (RF) signal, including;

a down-conversion circuit configured to produce a down-converted signal;

an analog-to-digital converter (ADC), coupled to an output of said down-conversion circuit, configured to digitize said down-converted signal;

a first demodulation circuit, coupled to an output of said ADC, configured to demodulate said digitized down-converted signal using a first demodulation method, wherein said first demodulation circuit includes a Motion Picture Expert Group (MPEG) decoder;

a second demodulation circuit, coupled to said output of said ADC, configured to demodulate said digitized down-converted signal using a second demodulation method, wherein said second demodulation circuit comprises;

an Audio/Video (A/V) processor configured to receive an input from said MPEG decoder,

a video encoder coupled to a first output of said A/V processor, and

an audio encoder coupled to a second output of said A/V processor; and

an upstream power amplifier disposed on said common semiconductor substrate.

2. The integrated set-top box of claim 1, further comprising:

a multiplexer coupled between said output of said down-conversion circuit and an input of said ADC.

3. The integrated set-top box of claim 1, further comprising:

a demultiplexer coupled between said output of said ADC and an input of said first demodulation circuit.

4. The integrated set-top box of claim 1, further comprising:

an in-phase/quadrature-phase (I/Q) Error Detection circuit configured to determine an I/Q error of said down-converted signal.

5. The integrated set-top box of claim 4, further comprising:

a local oscillator circuit configured to generate a quadrature local oscillator signal based on an output of said I/Q error detection circuit.

6. The integrated set-top box of claim 5, wherein said local oscillator circuit is configured to correct any I/Q phase imbalance determined by said I/Q error detection circuit.

7. The integrated set-top box of claim 5, wherein said local oscillator circuit comprises:

a direct digital frequency synthesizer (DDFS) configured to produce a digital representation of said quadrature local oscillator signal; and

a pair of digital-to-analog converters (DACs) that are coupled to quadrature outputs of said DDFS.

8. The integrated set-top box of claim 7, wherein said local oscillator circuit comprises:

a pair of low pass filters (LPFs) coupled to corresponding outputs of said pair of DACs; and

a Phase-Locked Loop (PLL), coupled to said outputs of said pair of DACs, said PLL being configured to multiply a frequency of said outputs of said pair of DACs to produce said quadrature local oscillator signal.

9. The integrated set-top box of claim 7, further comprising:

a memory coupled to said DDFS.

10. The integrated set-top box of claim 9, wherein said DDFS comprises:

a phase accumulator configured to receive phase information relating to said quadrature local oscillator signal with each successive clock cycle of said local oscillator circuit; and

a phase-to-sine converter configured to convert said phase information received from said memory into a digitized sinusoidal waveform.

11. The integrated set-top box of claim 1, wherein said MPEG decoder is configured to generate an MPEG output from said digitized down-converted signal, and wherein said second demodulation circuit is configured to generate an A/V output from said MPEG output.

12. The integrated set-top box of claim 1, wherein said first demodulation circuit comprises:

a nyquist filter coupled to said output of said ADC;

a symbol timing circuit coupled to an output of said nyquist filter; and

an equalizer coupled to an output of said symbol timing circuit and said MPEG decoder.

13. The integrated set-top box of claim 1, wherein said second demodulation circuit comprises:

an IF demodulator coupled to said output of said ADC;

a comb filter coupled to an output of said IF demodulator; and

a de-emphasis module coupled to said output of said IF demodulator.

14. The integrated set-top box of claim 13, wherein said A/V processor is coupled to an output of said first demodulation circuit, an output of said comb filter, and an output of said de-emphasis module.

15. The integrated set-top box of claim 1, wherein said first demodulation method is quadrature amplitude demodulation, and wherein said second demodulation method is National Television System Committee (NTSC) demodulation.

16. The integrated set-top box of claim 1, wherein said second demodulation circuit is further configured to extract an audio and video output from said input.

17. The integrated set-top box of claim 16, wherein said A/V processor is configured to extract said audio and video output from said input.

18. An integrated set-top box, comprising:

a common semiconductor substrate;

a down-stream path disposed on said common semiconductor substrate configured to down-convert a radio frequency (RF) signal, said down-stream path including;

a tuner configured to down-convert said RF signal; and

a down-conversion circuit configured to produce a down-converted signal;

a first demodulation circuit configured to demodulate said down-converted signal using a first demodulation method, wherein said first demodulation circuit includes a Motion Picture Expert Group (MPEG) decoder configured to generate an MPEG output;

a second demodulation circuit configured to demodulate said down-converted signal using a second demodulation method, wherein said second demodulation circuit comprises;

an Audio/Video (A/V) processor configured to directly receive said MPEG output from said MPEG decoder,

a video encoder directly coupled to a first output of said A/V processor, and

an audio encoder directly coupled to a second output of said A/V processor; and

an upstream power amplifier disposed on said common semiconductor substrate.

19. An integrated set-top box, comprising:

a common semiconductor substrate;

a down-stream path disposed on said common semiconductor substrate configured to down-convert a radio frequency (RF) signal, said down-stream path including;

a quadrature down-conversion circuit configured to produce a quadrature down-converted signal by mixing said RF signal with a quadrature local oscillator signal; and

a first demodulation circuit configured to demodulate said quadrature down-converted signal using quadrature amplitude demodulation, wherein said first demodulation circuit includes a Motion Picture Expert Group (MPEG) decoder configured to generate an MPEG signal;

a second demodulation circuit, configured to demodulate said quadrature down-converted signal using National Television System Committee (NTSC) demodulation, wherein said second demodulation circuit comprises;

a comb filter;

a de-emphasis module;

an Audio/Video (A/V) processor coupled to an output of said first demodulation circuit, an output of said comb filter, and an output of said de-emphasis module, wherein said A/V processor is configured to receive said MPEG signal from said MPEG decoder,

a video encoder coupled to a fist output of said A/V processor, and

an audio encoder coupled to a second output of said A/V processor; and

an upstream power amplifier disposed on said common semiconductor substrate.