Method and system for template assisted wafer bonding using pedestals

• US 8,735,191 B2
• Filed: 01/03/2013
• Issued: 05/27/2014
• Est. Priority Date: 01/04/2012
• Status: Active Grant

• Current Assignee: Skorpios Technologies Inc.
• Original Assignee: Skorpios Technologies Inc.
• Inventors: Marchena, Elton
• Primary Examiner(s): Geyer, Scott B
• Application Number:
  US13/733,337
• Publication Number:
  US 20130189804A1
• Time in Patent Office: 509 Days
• Field of Search: None
• US Class Current: 438/28
• CPC Class Codes: G02B 6/13 Integrated optical circuits characterised by the manufacturing method
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01S 5/0215 Bonding to the substrate
• CPC Class Codes: H01S 5/3013 AIIIBV compounds

Abstract

A method of fabricating a composite semiconductor structure includes providing a first substrate comprising a first material and having a first surface and forming a plurality of pedestals extending to a predetermined height in a direction normal to the first surface. The method also includes attaching a plurality of elements comprising a second material to each of the plurality of pedestals, providing a second substrate having one or more structures disposed thereon, and aligning the first substrate and the second substrate. The method further includes joining the first substrate and the second substrate to form the composite substrate structure and removing at least a portion of the first substrate from the composite substrate structure.

Claims

1. A method of fabricating a composite semiconductor structure, the method comprising:

providing a first substrate comprising a first material and having a first surface;

forming a plurality of pedestals extending to a predetermined height in a direction normal to the first surface;

attaching a plurality of elements comprising a second material to each of the plurality of pedestals;

providing a second substrate having one or more structures disposed thereon;

aligning the first substrate and the second substrate;

joining the first substrate and the second substrate to form the composite substrate structure; and

removing at least a portion of the first substrate from the composite substrate structure.

2. The method of claim 1 further comprising forming a wafer splitting region in the first substrate.

3. The method of claim 2 wherein the wafer splitting region comprises an implanted region.

4. The method of claim 3 wherein the implanted region comprises at least one of hydrogen, helium, or boron.

5. The method of claim 1 wherein forming the plurality of pedestals comprises a masking and etching process.

6. The method of claim 1 wherein the second material comprises at least one of III-V materials, ferromagnetic materials, or nonlinear optical materials.

7. The method of claim 1 wherein the one or more structures on the second substrate comprise at least one of optical elements or integrated circuits.

8. The method of claim 1 wherein the second substrate comprises a plurality of recessed regions and aligning the first substrate and the second substrate comprises inserting one or more of the plurality of elements into the plurality of recessed regions.

9. The method of claim 1 wherein removing at least a portion of the first substrate from the composite substrate structure comprises using a wafer splitting process.

10. The method of claim 1 wherein the second substrate comprises a plurality of device regions and joining the first substrate and the second substrate to form the composite substrate structure comprises forming an unbonded region adjacent to the plurality of device regions.

11. The method of claim 10 wherein the plurality of device regions comprise at least one of a waveguide, an electronic device, an optical device, or an integrated circuit.

12. A method of fabricating a composite semiconductor structure, the method comprising:

providing an SOI substrate including a plurality of silicon-based devices;

providing a plurality of photonic dies, each photonic die including one or more photonics devices;

providing an assembly substrate having a plurality of pedestals extending to a predetermined height from the assembly substrate;

mounting each of the plurality of photonic dies on one of the plurality of pedestals;

aligning the SOI substrate and the assembly substrate; and

joining the SOI substrate and the assembly substrate to form the composite substrate structure.

13. The method of claim 12 further comprising removing at least a portion of the assembly substrate from the composite substrate structure.

14. The method of claim 12 wherein providing a plurality of photonic dies comprises:

providing a compound semiconductor substrate including a plurality of photonic devices; and

dicing the compound semiconductor substrate to provide the plurality of photonic dies.

15. The method of claim 14 wherein the compound semiconductor substrate comprises a III-V wafer.

16. The method of claim 14 wherein the compound semiconductor substrate further includes electronic devices.

17. The method of claim 12 wherein the plurality of silicon-based devices comprise CMOS devices.

18. The method of claim 12 wherein the one or more photonic devices include at least one of a laser, a detector, or a modulator.

19. The method of claim 12 wherein mounting each of the plurality of photonic dies on one of the plurality of pedestals is performed after formation of the plurality of pedestals on the assembly substrate.

20. The method of claim 12 wherein providing the assembly substrate comprises:

oxidizing a silicon substrate; and

implanting the oxidized silicon substrate to form an implant region disposed between a top of the plurality of pedestals and the silicon substrate.