Method for manufacturing a semiconductor device including an impurity-doped silicon film

• US 8,735,230 B2
• Filed: 06/19/2007
• Issued: 05/27/2014
• Est. Priority Date: 06/20/2006
• Status: Expired due to Fees

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Inventors: Saino, Kanta
• Primary Examiner(s): MITCHELL, JAMES M
• Application Number:
  US11/765,116
• Publication Number:
  US 20070290259A1
• Time in Patent Office: 2,534 Days
• Field of Search: 438/259, 438/270, 438/157, 438/176, 438/195
• US Class Current: 438/157
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A process for manufacturing a semiconductor device consecutively includes forming a recess in the surface region of a silicon substrate, forming a gate insulation film on the surface of the recess, depositing a silicon electrode film including an oxygen-mixed layer extending parallel to the surface of the recess, injecting impurities into silicon the electrode film 17, and heat-treating the silicon electrode film to diffuse impurities.

Claims

1. A method for manufacturing a semiconductor device including a recessed-channel MOSFET, comprising:

forming a recess in a surface region of a semiconductor substrate, said recess having a plurality of surfaces;

forming a gate insulation film on said plurality of surfaces of said recess;

forming a silicon electrode on said gate insulation film by forming an oxygen-mixed layer on a first silicon electrode film, said oxygen-mixed layer being substantially parallel to each of said plurality of surfaces of said recess and being covered by a second silicon electrode film to fill said recess;

injecting impurities in said second silicon electrode film; and

heat-treating said first and second silicon electrode film to diffuse said impurities.

2. The method according to claim 1, wherein a distance between said surface of said recess and said oxygen-mixed layer is equal to or less than half a minimum width of said recess.

3. The method according to claim 1, wherein said impurities are of n-type.

4. The method according to claim 1, wherein said impurities are of p-type.

5. The method according to claim 1, wherein said heat-treating crystallizes said first silicon electrode film and said second silicon electrode film and forms a crystal grain interface, with said oxygen-mixed layer as a boundary.

6. The method according to claim 1, wherein a thickness of said first silicon electrode film is equal to or less than half a minimum width of said recess.

7. The method according to claim 1, wherein a thickness of said oxygen-mixed layer is formed by performing a thermal oxidation of a top surface of said first silicon electrode film.

8. The method according to claim 1, wherein said first silicon electrode film, said oxygen-mixed layer and said second silicon electrode film constitute a silicon electrode.

9. The method according to claim 1, wherein said first and said second silicon electrode films are formed in an amorphous state.