Integrated circuit metal gate structure and method of fabrication

• US 8,735,235 B2
• Filed: 11/21/2008
• Issued: 05/27/2014
• Est. Priority Date: 08/20/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry, Thei, Kong-Beng, Yeh, Chiung-Han, Liang, Mong-Song, Wu, Ming-Yuan
• Primary Examiner(s): Vu, David
• Application Number:
  US12/276,015
• Publication Number:
  US 20100044783A1
• Time in Patent Office: 2,013 Days
• Field of Search: 438/183, 438/595, 438/596, 438/652, 438/692, 438/700, 438/701, 257/407, 257/412, 257/E21.444, 257/E21.453
• US Class Current: 438/183
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate.

Claims

1. A method of fabricating a semiconductor device, comprising:

providing a substrate including an insulating layer, a dummy gate structure, spacer elements adjacent the dummy gate structure, and a contact etch stop layer (CESL) surrounding the spacer elements and dummy gate structure;

forming a trench in the insulating layer, wherein the trench has a first width and is formed by removing the dummy gate structure;

modifying the profile of the trench after removing the dummy gate structure by removing a portion of the spacer elements without removing the CESL, wherein the modifying includes providing a first portion of the trench with a second width, and a second portion of the trench with the first width, the second width being greater than the first width and wherein the modified trench includes a sidewall having an upper portion that is oblique to and contiguous with a lower portion of the sidewall, the lower portion being substantially perpendicular the substrate; and

forming a metal gate in the trench having the modified profile.

2. The method of claim 1, wherein the modifying the profile of the trench includes a sputtering process.

3. The method of claim 1, wherein the modifying the profile of the trench includes a plasma process containing an inert gas.

4. The method of claim 1, wherein the modifying the profile of the trench includes a sputtering process containing argon.

5. The method of claim 1, further comprising:

forming a high-k dielectric layer, wherein the metal gate is formed above the high-k dielectric layer.

6. The method of claim 1, wherein the upper portion is substantially linear.

7. The method of claim 1, wherein the upper portion is curved.

8. The method of claim 1, wherein the forming the trench includes removing dielectric material from the substrate.

9. A method of semiconductor fabrication, comprising:

providing a semiconductor substrate;

forming a dummy gate structure on the substrate, wherein the dummy gate structure includes polysilicon;

forming a spacer on the substrate adjacent the dummy gate structure;

forming a contact etch stop layer (CESL) surrounding the dummy gate structure and the spacer;

removing the dummy gate structure to form a trench having a top portion and a bottom portion, wherein the top portion and the bottom portion are of a first width;

increasing the width of the top portion of the trench to provide a second width after removing the dummy gate structure, wherein the increasing the width includes etching a portion of the spacer and providing substantially no etching of the CESL, and wherein the increasing the width provides a modified trench including a sidewall having an upper portion that is oblique to and is directly connected to a lower portion of the sidewall, the lower portion being substantially perpendicular the substrate; and

forming a gate in the trench including the second width, wherein the forming the gate includes depositing a first metal layer into the trench.

10. The method of claim 9, wherein the first metal layer includes nitrogen, carbon, or combination thereof.

11. The method of claim 9, wherein the increasing the width of the top portion of the trench includes a sputtering process, a reactive ion etch process, a plasma etch process, or a combination thereof.

12. The method of claim 9, further comprising:

forming a high dielectric constant (high k) gate dielectric layer on the substrate underlying the dummy gate structure.

13. A method, comprising:

providing a semiconductor substrate having a dummy gate formed thereon;

forming a contact etch stop layer (CESL) on the semiconductor substrate including surrounding the dummy gate structure, wherein the CESL has a top surface;

forming an interlayer dielectric (ILD) layer on and around the CESL, wherein the ILD layer has a top surface substantially coplanar with the top surface of the CESL;

forming a trench by removing the dummy gate, wherein the trench has sidewalls substantially perpendicular to the semiconductor substrate;

etching a top portion of the sidewalls of the trench, wherein the etching provides an etched trench having a first portion and a second portion, wherein the first portion has a greater width than the second portion, and wherein the first portion and the second portion sidewalls are contiguous, wherein after the etching surface the top surface of the CESL remains substantially co-planar the top surface of the ILD layer; and

forming a gate in the etched trench.

14. The method of claim 13, wherein the etching the top portion of the trench includes a sputtering process, a reactive ion etch process, a plasma etch process, or a combination thereof.

15. The method of claim 13, wherein the second portion of the etched trench has sidewalls substantially perpendicular to the semiconductor substrate.