Method for forming semiconductor structure having TiN layer

• US 8,735,269 B1
• Filed: 01/15/2013
• Issued: 05/27/2014
• Est. Priority Date: 01/15/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Sun, Chi-Yuan, Chen, Chien-Hao, Huang, Hsin-Fu, Tsai, Min-Chuan, Chen, Wei-Yu, Hsu, Chi-Mao, Cheng, Tsun-Min, Lin, Chin-Fu
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): ISAAC, STANETTA D
• Application Number:
  US13/741,402
• Time in Patent Office: 497 Days
• Field of Search: None
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

The method for forming a semiconductor structure includes first providing a substrate. Then, a TiN layer is formed on the substrate at a rate between 0.3 and 0.8 angstrom/second. Finally, a poly-silicon layer is formed directly on the TiN layer. Since the TiN in the barrier layer is formed at a low rate so as to obtain a good quality, the defects in the TiN layer or the defects on the above layer, such as gate dummy layer or gate cap layer, can be avoided.

Claims

1. A method for forming a semiconductor structure having a TiN layer, comprising:

providing a substrate;

forming a TiN layer on the substrate at a rate between 0.3 and 0.8 angstrom/second; and

forming a poly-silicon layer directly on the TiN layer.

2. The method for forming the semiconductor structure according to claim 1, wherein the TiN layer is formed at a rate between 0.4 and 0.6 angstrom/second.

3. The method for forming the semiconductor structure according to claim 1, wherein the TiN layer is formed by a PVD process.

4. The method for forming the semiconductor structure according to claim 3, wherein the PVD process is carried out by using a DC/RF power of 500/600 W.

5. The method for forming the semiconductor structure according to claim 3, wherein the PVD process is carried out by supplying 0/60 sccm of Ar/N₂ gas.

6. The method for forming the semiconductor structure according to claim 1, wherein the PVD process is by carried out by supplying 20/40 sccm of Ar/N₂ gas.

7. The method for forming the semiconductor structure according to claim 1, wherein the TiN layer is formed by a CVD process.

8. The method for forming the semiconductor structure according to claim 1, wherein the TiN has a thickness substantially between 10 and 30 angstroms.

9. The method for forming the semiconductor structure according to claim 1, wherein the semiconductor structure comprises a MOS.

10. The method for forming the semiconductor structure according to claim 9, wherein the TiN layer is used as a barrier layer of the MOS and the poly-silicon layer is used as a dummy layer of the MOS.

11. The method for forming the semiconductor structure according to claim 1, wherein before forming the TiN layer, further comprising:

forming a dielectric layer on the substrate, wherein the TiN layer is directly formed on the dielectric layer.

12. The method for forming the semiconductor structure according to claim 11, wherein the dielectric layer has a dielectric constant substantially greater than 20.

13. The method for forming the semiconductor structure according to claim 11, further comprising patterning the poly-silicon layer, the TiN layer and the dielectric layer.

14. The method for forming the semiconductor structure according to claim 13, wherein after the patterning process, the poly-silicon layer on the TiN layer is removed.