Method of semiconductor integrated circuit fabrication
First Claim
1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising:
- providing a substrate;
depositing a conductive layer on the substrate;
forming a patterned hard mask on the conductive layer to define a horizontal interconnection region;
forming a patterned photoresist on the conductive layer to define a vertical interconnection region;
forming a local metal catalyst layer on the conductive layer in the vertical interconnection region;
growing a plurality of carbon nanotubes (CNTs) from the local metal catalyst layer;
etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features; and
depositing an inter-level dielectric (ILD) layer between the metal features.
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Accused Products
Abstract
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A conductive layer is deposited on the substrate. A patterned hard mask is formed on the conductive layer and then a patterned photoresist is formed on the patterned hard mask and the conductive layer. A local metal catalyst layer is formed on the conductive layer in the openings of the patterned photoresist. Carbon nanotubes (CNTs) are grown from the local metal catalyst layer. The conductive layer is etched by using the CNTs and the patterned hard mask as etching mask to form metal features. An inter-level dielectric (ILD) layer is deposited between metal features.
13 Citations
19 Claims
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1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising:
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providing a substrate; depositing a conductive layer on the substrate; forming a patterned hard mask on the conductive layer to define a horizontal interconnection region; forming a patterned photoresist on the conductive layer to define a vertical interconnection region; forming a local metal catalyst layer on the conductive layer in the vertical interconnection region; growing a plurality of carbon nanotubes (CNTs) from the local metal catalyst layer; etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features; and depositing an inter-level dielectric (ILD) layer between the metal features. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for fabricating a semiconductor integrated circuit (IC), the method comprising:
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providing a substrate having a conductive feature; depositing a conductive layer on the substrate; depositing a carbon-containing hard mask on the conductive layer; patterning the carbon-containing hard mask to define a horizontal interconnection region on the conductive layer; coating a photoresist on the patterned carbon-containing hard mask and the conductive layer; patterning the photoresist to have an opening to expose at least a portion of the conductive layer such that the portion aligns to the conductive feature on the substrate; depositing a local metal catalyst layer on the conductive layer in the photoresist opening; removing the patterned photoresist; after removing the patterned photoresist, growing a plurality of carbon nanotubes (CNTs) from the local metal catalyst layer; etching the conductive layer by using the CNTs and the patterned hard mask as etching mask to form metal features in both horizontal and vertical interconnection regions; and depositing an inter-level dielectric (ILD) layer between metal features on the substrate. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification