Method for providing electrical connections to spaced conductive lines

• US 8,735,285 B2
• Filed: 12/04/2013
• Issued: 05/27/2014
• Est. Priority Date: 05/20/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej, Sills, Scott
• Primary Examiner(s): Coleman, William D
• Application Number:
  US14/096,052
• Publication Number:
  US 20140094026A1
• Time in Patent Office: 174 Days
• Field of Search: 438/666
• US Class Current: 438/666
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2224/06138 being disposed in a single wiring level, i.e. planar layout
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines

Abstract

An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

Claims

1. A method of fabricating an integrated circuit structure on a support structure, the method comprising:

forming a plurality of linearly extending material stack lines each comprising a polysilicon material, a metal silicide material, and an oxide top material;

cutting the material stack lines at an angle relative a linearly extending direction to form respective angled end faces at each of the material stack lines, the respective angled end faces being spaced in the linearly extending direction; and

forming an electrical contact landing pad as an extension of each of the material stack lines at each respective angled end face.

2. The method of claim 1, wherein the material stack lines are parallel material stack lines.

3. The method of claim 1, wherein the respective extensions are formed using the polysilicon as a seed to grow the electrical contact landing pad.

4. The method of claim 1, wherein the respective extensions are formed using the metal silicide as a seed to grow the electrical contact landing pad.

5. The method of claim 1, wherein the respective extensions are formed using the metal silicide or polysilicon as a seed to grow the electrical contact landing pad using electroless plating or selective chemical vapor deposition or atomic layer deposition processes.

6. The method of claim 1, further comprising:

depositing an insulating material over the electrical contact landing pad;

forming a via in the insulating material;

depositing a conductive material in the via.

7. The method of claim 1, wherein the respective extensions are isotropically grown from the respective angled end faces.

8. The method of claim 1, wherein the respective extensions are anisotropically grown from the respective angled end faces.

9. The method of claim 1, wherein the angled end faces are cut using a mask and etching process to form the angled end faces of the parallel material lines simultaneously.

10. The method of claim 1, wherein the forming a plurality of linearly extending material stack lines comprises:

forming a gate oxide material over a substrate;

forming the polysilicon material over the gate oxide;

forming the metal silicide material over the polysilicon;

forming the oxide top material over the metal silicide;

forming a plurality of mask lines over the oxide top material using a block copolymer self-assembly technique; and

using the mask lines to etch at least the polysilicon material, the metal silicide material, and the oxide top material.

11. The method of claim 1, wherein the material stack lines have a half pitch of 20 nm or less.

12. The method of claim 1, wherein the angle is between 5 degrees and 30 degrees relative to the linearly extending direction.

13. The method of claim 2, further comprising covering the parallel material lines with an encapsulation insulating material prior to cutting the parallel material lines.

14. The method of claim 13, further comprising removing a portion of the encapsulation insulating material from a portion of the material stack lines proximate the respective angled end faces prior to forming the respective electrical contact landing pads.

15. A method of fabricating an integrated circuit structure, the method comprising:

forming a gate oxide material over a substrate;

forming a polysilicon material over the gate oxide material;

forming a metal silicide material over the polysilicon material;

forming an oxide top material over the metal silicide material;

forming a plurality of linearly extending parallel material lines over the oxide top material;

cutting the parallel material lines at an angle relative the linearly extending direction to form respective angled end faces at each of the parallel material lines, the respective angled end faces being spaced in the linearly extending direction;

forming an extension of each of the parallel material lines at each respective angled end face;

etching at least the polysilicon material, metal silicide material and oxide top material using the parallel material lines and respective extensions as an etch mask to form conductive lines having respective electrical contact landing pad areas.

16. The method of claim 15, wherein the angled end faces are cut using a mask and etching process to form the angled end faces of the parallel material lines simultaneously.

17. The method of claim 15, wherein the angle is between 5 degrees and 30 degrees relative to the linearly extending direction.

18. The method of claim 15, wherein the parallel material lines are formed from a processed block copolymer.

19. The method of claim 15, wherein the parallel material lines are formed using a photolithographic technique.

20. The method of claim 15, wherein the forming the extension includes using at least a portion of the material line at the angled end face as a seed, and growing the contact landing pad masks from the seed via selective deposition of an extension material.