Semiconductor processing methods

• US 8,735,292 B2
• Filed: 04/08/2013
• Issued: 05/27/2014
• Est. Priority Date: 04/11/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Liu-Norrod, Junting, Ping, Er-Xuan, Takedai, Seiichi
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): STEVENSON, ANDRE C
• Application Number:
  US13/858,800
• Publication Number:
  US 20130237056A1
• Time in Patent Office: 414 Days
• Field of Search: None
• US Class Current: 438/689
• CPC Class Codes: C23C 18/1605 by masking
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/03616 Chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

Claims

1. A semiconductor processing method, comprising:

forming a substrate which comprises a monocrystalline silicon-containing semiconductor substrate to comprise an electrically conductive bond pad supporting layer along a front side of the substrate, and to comprise a silicon nitride passivation layer over the bond pad supporting layer;

the semiconductor substrate comprising a back side in opposing relation to the front side;

the back side having an exposed surface, and the front side having an exposed surface comprising a surface of the silicon nitride passivation layer;

utilizing plasma-enhanced atomic layer deposition to simultaneously deposit insulative material across the front side exposed surface and across the back side exposed surface;

the plasma-enhanced atomic layer deposition being conducted at a temperature of from at least about 300°

C. to less than or equal to about 500°

C. to activate hydrogen in the silicon nitride passivation layer during the deposition;

etching an opening that extends through the insulative material and through the silicon nitride passivation layer to expose a region of the bond pad supporting layer; and

plating conductive material within the opening and directly on the bond pad supporting layer, the conductive material comprising one or more of nickel, palladium and gold.

2. A semiconductor processing method, comprising:

forming a monocrystalline silicon-containing semiconductor substrate to comprise at least one level of integrated circuitry along its front side, and to comprise an electrically conductive bond pad supporting layer over the integrated circuitry;

the semiconductor substrate comprising a back side in opposing relation to the front side;

the back side having an exposed surface;

forming a passivation oxide over the bond pad supporting layer;

forming a passivation nitride over the passivation oxide;

utilizing plasma-enhanced atomic layer deposition to simultaneously deposit a composition across a surface of the passivation nitride and across the back side surface;

the composition deposited across the front side surface being a first layer of the composition, and the composition deposited across the back side surface being a second layer of the composition;

the plasma-enhanced atomic layer deposition being conducted at a temperature less than or equal to about 500°

C. but high enough to thermally treat the passivation nitride to cause hydrogen migration from the passivation nitride;

forming a polyimide-containing layer over the first layer of the composition;

etching a pattern of openings extending through the polyimide-containing layer, through the first layer of the composition and through the passivation nitride to expose a region of the bond pad supporting layer; and

plating conductive material within the opening and directly on the bond pad supporting layer, the conductive material within the opening comprising one or more of nickel, palladium and gold.

3. The method of claim 2 wherein the plated conductive material comprises nickel.

4. The method of claim 2 wherein the plated conductive material comprises palladium.

5. The method of claim 2 wherein the plated conductive material comprises gold.

6. The method of claim 2 wherein the polyimide-containing layer comprises photosensitive polyimide.