Semiconductor device including oxide semiconductor

• US 8,735,884 B2
• Filed: 10/01/2012
• Issued: 05/27/2014
• Est. Priority Date: 07/03/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakata, Junichiro, Sasaki, Toshinari, Hosoba, Miyuki
• Primary Examiner(s): Tran, Thanh Y
• Application Number:
  US13/632,709
• Publication Number:
  US 20130037799A1
• Time in Patent Office: 603 Days
• Field of Search: 257/59, 257/72, 257/257, 257/258, 257/390, 257/391, 257/368, 257/443, 257/431, 257/448, 257/745, 257/743, 257/751, 257/752, 257/753, 257/756, 257/758, 257/759, 257/760, 257/249, 257/250, 257/43, 257/79, 257/80, 257/81, 257/82, 257/83, 257/84, 257/99, 257/100, 257/103, 257/432, 257/433, 438/30, 438/104, 438/43, 438/158, 438/59, 438/66, 438/149, 438/157, 438/347, 438/151, 438/142, 438/176, 438/195, 438/277, 438/283, 438/587, 438/22, 438/26, 438/39, 438/42, 438/46, 438/128
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Claims

1. A semiconductor device comprising:

a first control line;

a second control line; and

a transistor,

wherein the transistor comprises;

a first conductive layer;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer over the first conductive layer;

a second conductive layer and a third conductive layer over and in contact with the oxide semiconductor layer;

a second insulating layer over and in contact with the oxide semiconductor layer, the second conductive layer, and the third conductive layer; and

a fourth conductive layer over the second insulating layer,

wherein the first conductive layer is electrically connected to the first control line, and

wherein the fourth conductive layer is electrically connected to the second control line.

2. The semiconductor device according to claim 1, wherein a width of the first conductive layer is larger than a width of the fourth conductive layer.

3. The semiconductor device according to claim 1, wherein a width of the fourth conductive layer is larger than a width of the first conductive layer.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium and zinc.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a microcrystalline region.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises an oxygen-excess region.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a depression.

8. The semiconductor device according to claim 1, wherein the second control line supplies a fixed potential.

9. The semiconductor device according to claim 1, wherein the semiconductor device is included in a pixel portion.

10. The semiconductor device according to claim 1, wherein the semiconductor device is included in a driver circuit.

11. A semiconductor device comprising:

a first control line;

a second control line; and

a transistor,

wherein the transistor comprises;

a first conductive layer;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer over the first conductive layer;

a second conductive layer and a third conductive layer over and in contact with the oxide semiconductor layer;

a second insulating layer over and in contact with the oxide semiconductor layer, the second conductive layer, and the third conductive layer;

a resin layer over the second insulating layer; and

a fourth conductive layer over the resin layer,

wherein the first conductive layer is electrically connected to the first control line, and

wherein the fourth conductive layer is electrically connected to the second control line.

12. The semiconductor device according to claim 11, wherein a width of the first conductive layer is larger than a width of the fourth conductive layer.

13. The semiconductor device according to claim 11, wherein a width of the fourth conductive layer is larger than a width of the first conductive layer.

14. The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises indium and zinc.

15. The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises a microcrystalline region.

16. The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises an oxygen-excess region.

17. The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises a depression.

18. The semiconductor device according to claim 11, wherein the second control line supplies a fixed potential.

19. The semiconductor device according to claim 11, wherein the semiconductor device is included in a pixel portion.

20. The semiconductor device according to claim 11, wherein the semiconductor device is included in a driver circuit.