Memories with memory arrays extending in opposite directions from a semiconductor and their formation

• US 8,735,902 B2
• Filed: 05/10/2010
• Issued: 05/27/2014
• Est. Priority Date: 05/10/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Zahurak, John, Kondoju, Siddartha, Liu, Haitao, Sinha, Nishant
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Bradford, Peter
• Application Number:
  US12/776,965
• Publication Number:
  US 20110272754A1
• Time in Patent Office: 1,478 Days
• Field of Search: 257/74, 257/278, 257/E21.614, 257/314
• US Class Current: 257/74
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/65 of memory structures of the ROM only type
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/00 EEPROM devices comprising charge-trapping gate insulators
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.

Claims

1. A memory, comprising:

a first array of first memory cells extending in a first direction from a first surface of a semiconductor material;

a first select gate coupled to a plurality of the first memory cells of the first array of first memory cells;

a second array of second memory cells extending in a second direction, opposite to the first direction, from a second surface of the semiconductor material; and

a second select gate coupled to a plurality of the second memory cells of the second array of second memory cells;

wherein the first array of first memory cells and the second array of second memory cells each comprise conductively doped regions in the semiconductor material;

wherein the semiconductor material extends from the first array of first memory cells to the second array of second memory cells; and

wherein a single source/drain region in the semiconductor material commonly couples both the first and the second select gates to a single data line and extends from the first array of first memory cells to the second array of second memory cells.

2. The memory of claim 1, wherein the first array of first memory cells is selected from a group consisting of a phase-change memory array, a resistive RAM memory array, an array of memory cells configured to be programmed as single-level cells, an array of memory cells configured to be programmed as multi-level cells, and a NAND memory array and the second array of second memory cells is selected from a group consisting of a phase-change memory array, a resistive RAM memory array, an array of memory cells configured to be programmed as single-level cells, an array of memory cells configured to be programmed as multi-level cells, and a NAND memory array.

3. The memory of claim 1, wherein the first array of first memory cells is a non-volatile memory array and the second array of second memory cells is a non-volatile memory array.

4. The memory of claim 1, wherein:

each of the first memory cells comprises;

a tunnel dielectric over the first surface of the semiconductor material;

a charge storage node over the tunnel dielectric;

an interlayer dielectric over the charge storage node; and

a control gate over the interlayer dielectric; and

each of the second memory cells comprises;

a tunnel dielectric over the second surface of the semiconductor material;

a charge storage node over the tunnel dielectric;

an interlayer dielectric over the charge storage node; and

a control gate over the interlayer dielectric.

5. The memory of claim 1, wherein the conductively doped regions of at least one of the first array of memory cells and the second array of memory cells form other source/drain regions in the semiconductor material.

6. The memory of claim 1, wherein the plurality of the first memory cells of the first array of first memory cells coupled to the first select gate comprises a string of the first memory cells of the first array of first memory cells coupled in series, and wherein the plurality of the second memory cells of the second array of second memory cells coupled to the second select gate comprises a string of the second memory cells of the second array of second memory cells coupled in series.

7. The memory of claim 1, wherein the first select gate extends in the first direction from the first surface of the semiconductor material, and wherein the second select gate extends in the second direction from the second surface of the semiconductor material.

8. A memory, comprising:

a first array of first memory cells extending in a first direction from a first surface of a semiconductor material; and

a second array of second memory cells extending in a second direction, opposite to the first direction, from a second surface of the semiconductor material; and

isolation regions that extend through a charge storage node and a tunnel dielectric of the first array of first memory cells, through the semiconductor material, and through a tunnel dielectric and a charge storage node of the second array of second memory cells;

wherein the first array of first memory cells and the second array of second memory cells each comprise conductively doped regions in the semiconductor material; and

wherein the semiconductor material extends from the first array of first memory cells to the second array of second memory cells.

9. The memory of claim 8, wherein the isolation regions terminate on or within interlayer dielectrics of the first array of first memory cells and of the second array of second memory cells.

10. A memory, comprising:

a first array of first memory cells extending in a first direction from a first surface of a semiconductor material; and

a second array of second memory cells extending in a second direction, opposite to the first direction, from a second surface of the semiconductor material; and

isolation regions that extend through a charge storage node and a tunnel dielectric of the first array of first memory cells, through the semiconductor material, between the conductively doped regions of the second array of second memory cells in the semiconductor material, and through an anti-fuse of the second array of second memory cells;

wherein the first array of first memory cells and the second array of second memory cells each comprise conductively doped regions in the semiconductor material; and

wherein the semiconductor material extends from the first array of first memory cells to the second array of second memory cells.

11. The memory of claim 10, wherein:

each of the first memory cells comprises;

a tunnel dielectric over the first surface of the semiconductor material;

a charge storage node over the tunnel dielectric;

an interlayer dielectric over the charge storage node; and

a control gate over the interlayer dielectric; and

each of the second memory cells comprises a portion of the anti-fuse of the second array of second memory cells.

12. The memory of claim 10, wherein the second array of second memory cells is a one-time programmable memory array.