Semiconductor device and method of manufacturing semiconductor device

• US 8,735,906 B2
• Filed: 04/05/2010
• Issued: 05/27/2014
• Est. Priority Date: 04/13/2009
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US13/259,344
• Publication Number:
  US 20120049202A1
• Time in Patent Office: 1,513 Days
• Field of Search: 257/77, 257/301, 257/139, 257/328, 257/330, 257/333, 438/99, 438/591, 438/440, 438/424
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The semiconductor device according to the present invention includes a semiconductor layer of a first conductivity type made of SiC, a body region of a second conductivity type formed on a surface layer portion of the semiconductor layer, a gate trench dug down from a surface of the semiconductor layer with a bottom surface formed on a portion of the semiconductor layer under the body region, source regions of the first conductivity type formed on a surface layer portion of the body region adjacently to side surfaces of the gate trench, a gate insulating film formed on the bottom surface and the side surfaces of the gate trench so that the thickness of a portion on the bottom surface is greater than the thickness of portions on the side surfaces, a gate electrode embedded in the gate trench through the gate insulating film, and an implantation layer formed on a portion of the semiconductor layer extending from the bottom surface of the gate trench to an intermediate portion of the semiconductor layer in the thickness direction by implantation of a second conductivity type impurity.

Claims

1. A semiconductor device comprising:

a semiconductor layer of a first conductivity type made of SiC;

a body region of a second conductivity type formed on a surface layer portion of the semiconductor layer;

a gate trench dug down from a surface of the semiconductor layer with a bottom surface formed on a portion of the semiconductor layer under the body region;

a plurality of source regions of the first conductivity type formed on a surface layer portion of the body region adjacent to side surfaces of the gate trench;

a gate insulating film formed on the bottom surface and side surfaces of the gate trench so that the thickness of a bottom portion on the bottom surface is greater than the thickness of side portions on the side surfaces;

a gate electrode embedded in the gate trench through the gate insulating film; and

an implantation layer formed on a portion of the semiconductor layer extending from the bottom surface of the gate trench to an intermediate portion of the semiconductor layer in the thickness direction by implantation of a second conductivity type impurity;

wherein side portions of the gate insulating film include at least one first portion adjacent to the plurality of source regions on the side surfaces of the gate trench and at least one second portion other than the at least one first portion thereof;

wherein a thickness T₁ of the first portions is greater than a thickness T₂ of the second portions;

wherein the first portions of the gate insulating film protrude along with the surface of the semiconductor layer on both of an inner side and an outer side of the gate trench with respect to the side surfaces of the gate trench inside the gate trench; and

wherein the ratio (T₁/T₂) of the thickness T₁ of the first portions of side portions to the thickness T₂ of the second portions thereof is greater than 1 and less than or equal to 3.

2. The semiconductor device according to claim 1, wherein the implantation layer is an active layer provided with conductivity by activation of the second conductivity type impurity.

3. The semiconductor device according to claim 1, wherein the ratio (T₃/T₂) of a thickness T₃ of the bottom portion of the gate insulating film to the thickness T₂ of the second portions of the side portions is 1 to 2.

4. The semiconductor device according to claim 1, wherein the surface of the semiconductor layer is an Si plane.

5. The semiconductor device according to claim 1, wherein the bottom surface of the gate trench includes inclined portions formed on both end portions of the side surfaces of the gate trench opposed to each other in the opposed direction and inclined from the respective lower ends of the side surfaces toward the surface of the semiconductor layer, and a parallel portion connecting lower ends of the inclined portions with each other and parallel to the surface of the semiconductor layer.

6. The semiconductor device according to claim 5, wherein the implantation layer is formed in contact with the whole area of the parallel portion.

7. The semiconductor device according to claim 1, wherein the depth of the implantation layer is 0.1 μ

m to 0.5 μ

m.

8. The semiconductor device according to claim 1, wherein the second conductivity type impurity concentration in the implantation layer is 1×

10¹⁶ cm<sup>−

3</sup> to 1×

10²¹ cm<sup>−

3</sup>.