Semiconductor devices

• US 8,735,974 B2
• Filed: 02/16/2010
• Issued: 05/27/2014
• Est. Priority Date: 02/16/2010
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Senoo, Masaru
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US13/579,440
• Publication Number:
  US 20120313164A1
• Time in Patent Office: 1,561 Days
• Field of Search: 257330-333, 257/E29.262, 438/259, 438/270
• US Class Current: 257/330
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

An object of the present application is to reduce the gate capacitance without lowering the withstand voltage of a semiconductor device and prevent generation of a leak current between main electrodes even when an oxide film is formed poorly. A semiconductor device of the present application comprises a gate electrode and a dummy gate electrode. The gate electrode is insulated from an emitter electrode and faces a part of a body region via an insulating film, the part of the body region separating a drift region and an emitter region from each other. The dummy gate electrode is electrically connected with the emitter electrode and is connected with the drift region and the body region via the insulating film. At least a part of the dummy gate electrode comprises a first conductive region of the same type as the drift region. In the dummy gate electrode, the emitter electrode is separated from the drift region by the first conductive region.

Claims

1. A semiconductor device comprising:

a first semiconductor region of a first conductive type;

a second semiconductor region of a second conductive type, the second semiconductor region being in contact with the first semiconductor region;

a third semiconductor region of the first conductive type, the third semiconductor region being in contact with the second semiconductor region and separated from the first semiconductor region by the second semiconductor region;

a fourth semiconductor region of the second conductive type, the fourth semiconductor region being in contact with the third semiconductor region and separated from the first and second semiconductor regions by the third semiconductor region;

a first main electrode electrically connected with the first semiconductor region;

a second main electrode electrically connected with the third and fourth semiconductor regions;

a gate electrode insulated from the second main electrode, the gate electrode being connected with the second, third and fourth semiconductor regions via a first insulating film, and opposing a part of the third semiconductor region via the first insulating film, the part of the third semiconductor region separating the fourth semiconductor region from the second semiconductor region; and

a conductive region electrically connected with the second main electrode, the conductive region being connected with the second and third semiconductor regions via a second insulating film, wherein

the conductive region comprises a first conductive region of the first conductive type, and a second conductive region of the second conductive type, the second conductive region being in contact with the first conductive region,

a second conductive type impurity concentration of the second conductive region is lower than that of the second semiconductor region, and

within the conductive region, the first conductive region separates the second main electrode from the second semiconductor region, the second main electrode is separated from the second conductive region by the first conductive region, and the second semiconductor region is separated from the first conductive region by the second conductive region.

2. The semiconductor device as in claim 1, wherein

the first conductive type is p type,

the second conductive type is n type, and

the first conductive region is in contact with the second main electrode, and is not in contact with the second insulating film.

3. The semiconductor device as in claim 1, wherein

the conductive region is further in contact with the fourth semiconductor region via the second insulating film, and opposes a part of the third semiconductor region via the second insulating film, the part of the third semiconductor region separating the fourth semiconductor region from the second semiconductor region.

4. The semiconductor device as in claim 3, wherein

the third semiconductor region is disposed below and lateral to the fourth semiconductor region,

the second semiconductor region is disposed below the third semiconductor region,

the first semiconductor region is disposed below the second semiconductor region,

the first main electrode is disposed below the first semiconductor region,

the second main electrode is disposed on an upper side of the third and fourth semiconductor regions,

the gate electrode is disposed within a first trench that penetrates the third semiconductor region from an upper surface of the fourth semiconductor region and reaches to the second semiconductor region, and

the conductive region is disposed within a second trench that penetrates the third semiconductor region and reaches to the second semiconductor region.

5. The semiconductor device as in claim 4, wherein

the second conductive region is disposed at a bottom of the second trench, the first conductive region is disposed on an upper side of the second conductive region, and

a boundary between the first conductive region and the second conductive region is at a same height as a boundary between the second semiconductor region and the third semiconductor region.

6. The semiconductor device as in claim 1, wherein

the third semiconductor region is disposed below and lateral to the fourth semiconductor region,

the second semiconductor region is disposed below the third semiconductor region,

the first semiconductor region is disposed below the second semiconductor region,

the first main electrode is disposed below the first semiconductor region,

the second main electrode is disposed on an upper side of the third and fourth semiconductor regions,

the gate electrode is disposed within a first trench that penetrates the third semiconductor region from an upper surface of the fourth semiconductor region and reaches to the second semiconductor region, and

the conductive region is disposed within a second trench that penetrates the third semiconductor regions and reaches to the second semiconductor region.

7. The semiconductor device as in claim 6, wherein

the second conductive region is disposed at a bottom of the second trench,

the first conductive region is disposed on an upper side of the second conductive region, and

a boundary between the first conductive region and the second conductive region is at a same height as a boundary between the second semiconductor region and the third semiconductor region.

8. The semiconductor device as in claim 1, wherein

the third semiconductor region is disposed below and lateral to the fourth semiconductor region,

the second semiconductor region is disposed below and lateral to the third semiconductor region,

the first semiconductor region is disposed below the second semiconductor region,

the first main electrode is disposed below the first semiconductor region,

the second main electrode is disposed on an upper side of the third and fourth semiconductor regions,

the gate electrode is in contact with upper surfaces of the fourth, third, and second semiconductor regions via the first insulating film, and

the conductive region is in contact with the upper surfaces of the third and second semiconductor regions via the second insulating film.

9. A semiconductor device comprising:

a first semiconductor region of a first conductive type;

a second semiconductor region of a second conductive type, the second semiconductor region being in contact with the first semiconductor region;

a third semiconductor region of the first conductive type, the third semiconductor region being in contact with the second semiconductor region and separated from the first semiconductor region by the second semiconductor region;

a fourth semiconductor region of the second conductive type, the fourth semiconductor region being in contact with the third semiconductor region and separated from the first and second semiconductor regions by the third semiconductor region;

a first main electrode electrically connected with the first semiconductor region;

a second main electrode electrically connected with the third and fourth semiconductor regions;

a gate electrode insulated from the second main electrode, the gate electrode being connected with the second, third and fourth semiconductor regions via a first insulating film, and opposing a part of the third semiconductor region via the first insulating film, the part of the third semiconductor region separating the fourth semiconductor region from the second semiconductor region; and

a conductive region electrically connected with the second main electrode, the conductive region being connected with the second and third semiconductor regions via a second insulating film, wherein

the conductive region comprises a first conductive region of the first conductive type, and a second conductive region of the second conductive type, the second conductive region being in contact with the first conductive region,

a second conductive type impurity concentration of the second conductive region is lower than that of the second semiconductor region,

the first conductive region separates the second main electrode from the second semiconductor region within the conductive region,

the third semiconductor region is disposed below and lateral to the fourth semiconductor region,

the second semiconductor region is disposed below the third semiconductor region,

the first semiconductor region is disposed below the second semiconductor region,

the first main electrode is disposed below the first semiconductor region,

the second main electrode is disposed on an upper side of the third and fourth semiconductor regions,

the gate electrode is disposed within a first trench that penetrates the third semiconductor region from an upper surface of the fourth semiconductor region and reaches to the second semiconductor region,

the conductive region is disposed within a second trench that penetrates the third semiconductor region and reaches to the second semiconductor region,

the second conductive region is disposed at a bottom of the second trench,

the first conductive region is disposed on an upper side of the second conductive region, and

a boundary between the first conductive region and the second conductive region is at a same height as a boundary between the second semiconductor region and the third semiconductor region.