Front side copper post joint structure for temporary bond in TSV application

• US 8,736,050 B2
• Filed: 07/07/2010
• Issued: 05/27/2014
• Est. Priority Date: 09/03/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Hon-Lin, Hsiao, Ching-Wen, Hsu, Kuo-Ching, Chen, Chen-Shien
• Primary Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US12/831,819
• Publication Number:
  US 20110049706A1
• Time in Patent Office: 1,420 Days
• Field of Search: None
• US Class Current: 257/737
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11823 Immersion coating, e.g. in a solder bath
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/119 Methods of manufacturing bump connectors involving a specific sequence of method steps
• CPC Class Codes: H01L 2224/11912 the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13027 the bump connector being offset with respect to the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13562 : On the entire exposed surface of the core
• CPC Class Codes: H01L 2224/1357 : Single coating layer
• CPC Class Codes: H01L 2224/13611 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/818 : Bonding techniques
• CPC Class Codes: H01L 23/3157 : Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate;

a conductive via (TSV) passing through the semiconductor substrate;

an interconnect structure overlying the semiconductor substrate;

a metal pad directly overlying the interconnect structure;

a first polyimide layer overlying the metal pad;

a second polyimide layer comprising a portion level with the interconnect structure, wherein the metal pad extends into the second polyimide layer and contacts the interconnect structure;

an under-bump-metallurgy (UBM) directly coupled to the metal pad;

a dielectric buffer layer between the first polyimide layer and the UBM, wherein the dielectric buffer layer comprises a first portion contacting the metal pad and a second portion over and separated from the metal pad; and

a copper-containing post overlying the UBM layer, wherein the copper post is electrically connected to the conductive via.

2. The integrated circuit structure of claim 1 further comprising:

a conductive barrier over the copper-containing post; and

a solder over the conductive barrier.

3. The integrated circuit structure of claim 1 further comprising a metallic layer on the copper-containing post, wherein the metallic layer comprises a first portion directly over the copper-containing post, and a second portion on a sidewall of the copper-containing post.

4. The integrated circuit structure of claim 1, wherein the metal pad is connected to the UBM through a conductive feature in the dielectric buffer layer.

5. The integrated circuit structure of claim 1, wherein the copper-containing post has a thickness less than about 60 μ

m.

6. An integrated circuit structure comprising:

a semiconductor substrate;

a conductive via extending from a front surface to a back surface of the semiconductor substrate;

an interconnect structure overlying the front surface of the semiconductor substrate, wherein the interconnect structure comprises copper;

an aluminum-containing pad overlying the semiconductor substrate;

a first polyimide layer over the aluminum-containing pad;

a second polyimide layer overlying the interconnect structure, the second polyimide layer having an upper surface coplanar with an upper surface of the aluminum-containing pad;

an under-bump-metallurgy (UBM) over and connected to the aluminum-containing pad;

a dielectric buffer layer between the first polyimide layer and the UBM, wherein the dielectric buffer layer comprises a first portion contacting the aluminum-containing pad and a second portion over and separated from the aluminum-containing pad; and

a copper-containing post overlying the front surface of the semiconductor substrate and electrically connected to the conductive via and the interconnect structure.

7. The integrated circuit structure of claim 6, wherein a thickness of the copper-containing post is between about 55 μ

m and about 30 μ

m.

8. The integrated circuit structure of claim 6, wherein the UBM comprises an extension extending into the first polyimide layer and electrically connected to the aluminum-containing pad.

9. The integrated circuit structure of claim 6 further comprising:

a conductive barrier over the copper-containing post; and

a solder over the conductive barrier.

10. The integrated circuit structure of claim 6 further comprising a metal finish on the copper-containing post, wherein the metal finish comprises a first portion directly over the copper-containing post, and a second portion on a sidewall of the copper-containing post.

11. The integrated circuit structure of claim 10, wherein the metal finish comprises a metal selected from the group consisting essentially of tin, nickel, palladium, gold, and combinations thereof.

12. An integrated circuit structure comprising:

a semiconductor substrate;

a conductive via extending from a front surface to a back surface of the semiconductor substrate;

an interconnect structure overlying the semiconductor substrate;

a metal pad directly overlying the interconnect structure;

an under-bump-metallurgy (UBM) directly coupled to the metal pad;

a pair of polyimide layers overlying the interconnect structure;

a dielectric buffer layer between the UBM and an uppermost layer of the pair of polyimide layers, wherein the dielectric buffer layer comprises a first portion contacting the metal pad and a second portion over the metal pad;

a copper-containing post over the UBM layer, wherein the copper post is electrically connected to the conductive via; and

a conductive barrier over the copper-containing post, wherein the conductive barrier, the copper-containing post, and the conductive via are electrically connected.

13. The integrated circuit structure of claim 12, wherein the UBM comprising a first portion coupled to the metal pad, and a second portion over the second portion of the dielectric buffer layer.

14. The integrated circuit structure of claim 12 further comprising a solder over the conductive barrier.