Device for reducing contact resistance of a metal

• US 8,736,056 B2
• Filed: 08/31/2012
• Issued: 05/27/2014
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Su, Hung-Wen, Lee, Ya-Lien
• Primary Examiner(s): Williams, A O
• Application Number:
  US13/601,223
• Publication Number:
  US 20140035143A1
• Time in Patent Office: 634 Days
• Field of Search: 257/751, 257/774, 257/773, 257/758, 257/E23.019, 257/E21.579, 257/E21.584
• US Class Current: 257/751
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes an atomic layer deposition (ALD) TaN or a chemical vapor deposition (CVD) TaN deposited on a side wall of the trench, a physical vapor deposition (PVD) Ta or a combination of the PVD Ta and a PVD TaN deposited on the ALD TaN or CVD TaN, and a Cu deposited on the PVD Ta or the combination of the PVD Ta and the PVD TaN deposited on the ALD TaN or the CVD TaN. The structure further includes a via integrated into the trench at bottom of the filled trench.

Claims

1. A structure for an integrated circuit, the structure comprising:

a substrate;

a cap layer deposited on the substrate;

a dielectric layer deposited on the cap layer; and

a trench embedded in the dielectric layer, wherein the trench includes;

an atomic layer deposition (ALD) TaN layer formed on a side wall of the trench, wherein the ALD TaN Layer has a greater concentration of nitrogen than tantalum;

a physical vapor deposition (PVD) Ta layer formed over the ALD TaN layer; and

a Cu-containing layer formed over the PVD Ta layer;

wherein an overall N/Ta ratio of the ALD TaN layer and the PVD Ta ranges from about 0.6 to about 1.0.

2. The structure of claim 1, wherein a N/Ta ratio of the ALD TaN layer ranges from about 2.3 to about 2.6.

3. The structure of claim 1, further comprising a via integrated into the trench at a bottom portion of the trench, wherein the via reaches to the cap layer.

4. The structure of claim 1, wherein a thickness of the ALD TaN layer ranges from about 5 to about 10 angstrom (Å

).

5. The structure of claim 1, wherein the trench further comprises a PVD TaN layer formed between the ALD TaN layer and the PVD Ta layer.

6. The structure of claim 5, wherein a N/Ta ratio of the PVD TaN layer ranges from about 0.3 to about 0.6.

7. The structure of claim 1, wherein the dielectric layer has a low-k material with a dielectric constant k ranging from about 2.6 to about 2.65.

8. The structure of claim 1, wherein an overall carbon (C) concentration of the ALD TaN layer and the PVD Ta layer ranges from about 0.2 to about 1 percent (%).

9. The structure of claim 1, wherein the PVD Ta layer comprises α

-Ta and β

-Ta.

10. A structure for an integrated circuit, the structure comprising:

a substrate;

a first cap layer formed over the substrate;

a first dielectric layer formed over the first cap layer;

a first trench embedded in the first dielectric layer, wherein the first trench includes;

a first atomic layer deposition (ALD) TaN layer deposited on bottom and sidewalls of the first trench, wherein the ALD TaN layer has a greater concentration of nitrogen than tantalum;

a first physical vapor deposition (PVD) Ta layer deposited over the first ALD TaN layer; and

a first Cu-containing layer formed over the first PVD Ta;

a second cap layer formed over the first dielectric layer;

a second dielectric layer formed over the first dielectric layer;

a second trench embedded in the second dielectric layer, wherein the second trench includes;

a second ALD TaN layer deposited on bottom and sidewalls of the second trench;

a second PVD Ta layer deposited over the second ALD TaN layer; and

a second Cu-containing layer formed over the PVD Ta layer; and

a via located between the first trench and the second trench, wherein the via is integrated into the first trench at a top portion of the first trench and integrated into the second trench at a bottom portion of the second trench.

11. The structure of claim 10, wherein the first and second trenches each further includes a PVD TaN layer formed between the corresponding ALD TaN layer and PVD Ta layer, wherein the PVD TaN layer has a greater concentration of tantalum than nitrogen.

12. The structure of claim 11, wherein a contact resistance (Rc) of the first trench to the second trench ranges from about 6 to about 11 Ohms (Ω

) while a critical dimension (CD) of the first trench changing ranges from about 0.05 to about 0.5 micrometer (μ

m).

13. The structure of claim 10, wherein a CD of the via ranges from about 0.025 to about 0.040 μ

m while a CD of the first trench or the second trench ranges from about 0.036 μ

m to about 1.0 μ

m.

14. The structure of claim 10, wherein a CD of the via ranges from about 0.040 to about 0.055 μ

m while a CD of the first trench or the second trench ranges from about 0.045 μ

m to about 1.0 μ

m.

15. The structure of claim 10, wherein a CD of the via ranges from about 0.055 to about 0.070 μ

m while a CD of the first trench or the second trench ranges from about 0.064 μ

m to about 1.0 μ

m.