PSOC architecture

• US 8,736,303 B2
• Filed: 12/16/2011
• Issued: 05/27/2014
• Est. Priority Date: 10/26/2000
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren, Mar, Monte
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US13/328,385
• Publication Number:
  US 20120086471A1
• Time in Patent Office: 893 Days
• Field of Search: None
• US Class Current: 326/41
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03K 19/08 using semiconductor devices H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.

Claims

1. A circuit, comprising:

a plurality of analog circuit blocks, each configured to provide at least one analog function; and

a programmable interconnect coupled to the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another, wherein the circuit is formed in an integrated circuit and wherein the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the integrated circuit, wherein the plurality of switches are configured in one or more multiplexer (MUX) circuits, the MUX circuits comprising MUX inputs and MUX outputs coupled to the analog circuit blocks.

2. The circuit of claim 1, further comprising at least one digital block comprising a plurality of digital blocks that each provides at least one digital function, and wherein the programmable interconnect is further coupled to the plurality of digital blocks and configurable to interconnect combinations of the plurality of digital blocks to one another.

3. The circuit of claim 1, wherein the one or more MUX circuits comprise block MUX circuits coupled to the analog circuits.

4. The circuit of claim 1, wherein the programmable interconnect is programmable to provide multiple signal paths between same analog circuit blocks.

5. The circuit of claim 1, wherein the analog circuit blocks are selected from the group of:

analog continuous time amplifiers and switched capacitor type circuits.

6. A circuit, comprising:

a programmable interconnect configurable to enable multiple signal routing between signal paths;

a plurality of analog circuit blocks formed in a same integrated circuit comprising inputs and outputs coupled to the signal paths, each analog block providing at least one analog function, wherein the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the same integrated circuit; and

an internal input/output (I/O) bus comprising bus lines coupled to the signal paths.

7. The circuit of claim 6, wherein the programmable interconnect is configurable to connect multiple analog blocks in series with one another.

8. The circuit of claim 6, further comprising at least one digital circuit block comprising a plurality of digital circuit blocks formed in the same integrated circuit comprising inputs and outputs coupled to the signal paths.

9. The circuit of claim 6, wherein each analog circuit block is programmable between at least one of a plurality of different analog functions.

10. The circuit of claim 6, wherein:

the same integrated circuit comprises at least one port as a signal connection point; and

the programmable interconnect is configurable to connect the at least one port to any of the analog circuit blocks.

11. The circuit of claim 10, wherein the programmable interconnect is configurable to provide an analog signal input path from the at least one port to any of the analog circuit blocks.

12. The circuit of claim 10, wherein the programmable interconnect is configurable to provide an analog signal output path from any of the analog circuit blocks to the at least one port.

13. A method, comprising:

providing a plurality of analog circuit blocks in an integrated circuit; and

providing a programmable interconnect configurable to at least enable combinations of analog circuit blocks to be interconnected to combine analog functions of the analog circuit blocks using a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the integrated circuit, wherein the plurality of switches are configured in one or more multiplexer (MUX) circuits, the MUX circuits comprising MUX inputs and MUX outputs coupled to the analog circuit blocks.

14. The method of claim 13, further comprising enabling any of the analog circuit blocks to be connected to at least one port that provides a signal connection point to the integrated circuit using the programmable interconnect.

15. The method of claim 13, further comprising:

providing at least one digital circuit block in the integrated circuit; and

enabling any of the digital circuit blocks to be interconnected to combine digital functions of the digital circuit blocks using the programmable interconnect.

16. The method of claim 13, further comprising enabling at least two analog circuit blocks to be coupled in series using the programmable interconnect.

17. The method of claim 13, further comprising enabling any of the analog circuit blocks to be connected to the at least one digital circuit block using the programmable interconnect.

18. The method of claim 13, further comprising providing an analog signal output path from any of the analog circuit blocks to the at least one port.