Semiconductor device

• US 8,736,315 B2
• Filed: 09/07/2012
• Issued: 05/27/2014
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/606,440
• Publication Number:
  US 20130082760A1
• Time in Patent Office: 627 Days
• Field of Search: 327108-112, 327/170, 327/379, 327389-391
• US Class Current: 327/108
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/14 Semiconductor devices, e.g. diodes
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03B 1/00 Details
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 3/00 Circuits for generating electric pulses; Monostable, bistable or multistable circuits H03K4/00 takes precedence; for digital function generators in computers G06F1/02

Abstract

Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Claims

1. A semiconductor device comprising:

a first wiring configured to be applied with a constant potential;

an input terminal and an output terminal;

first and second transistors each of which comprises a first terminal, a second terminal, and a gate; and

a capacitor comprising first and second electrodes,

wherein;

the first terminal, the second terminal, and the gate of the first transistor are electrically connected to the first wiring, the output terminal, and the gate of the second transistor, respectively;

the first terminal and the second terminal of the second transistor are electrically connected to the first wiring and the second electrode, respectively; and

the first electrode is electrically connected to the input terminal.

2. The semiconductor device according to claim 1, wherein the first and second transistors have the same conductivity type.

3. An inverter circuit comprising the semiconductor device according to claim 1.

4. The semiconductor device according to claim 1, wherein the first and second transistors comprise an oxide semiconductor.

5. An electronic device comprising the semiconductor device according to claim 1.

21. The semiconductor device according to claim 1, wherein the input terminal is configured to be applied with a first potential and a second potential which is different from the first potential.

22. The semiconductor device according to claim 1, wherein the output terminal is configured to output different two potentials in accordance with the potential applied to the input terminal.

23. The semiconductor device according to claim 1, wherein the second terminal of the first transistor and the output terminal exist in the same potential.

24. The semiconductor device according to claim 1, wherein the second terminal of the first transistor is directly connected to the output terminal.

6. A semiconductor device comprising:

a first wiring configured to be applied with a first constant potential;

a second wiring configured to be applied with a second constant potential;

an input terminal and an output terminal;

first to fifth transistors each of which comprises a first terminal, a second terminal, and a gate; and

a capacitor comprising first and second electrodes,

wherein;

the first terminal, the second terminal, and the gate of the first transistor are electrically connected to the first wiring, the output terminal, and the second terminal of the fifth transistor, respectively;

the first terminal, the second terminal, and the gate of the second transistor are electrically connected to the second wiring, the output terminal, and the input terminal, respectively;

the first terminal, the second terminal, and the gate of the third transistor are electrically connected to the first wiring, the second electrode, and the second terminal of the fifth transistor, respectively;

the first terminal, the second terminal, and the gate of the fourth transistor are electrically connected to the second wiring, the second electrode, and the input terminal, respectively;

the first terminal and the gate of the fifth transistor are electrically connected to the second wiring and the input terminal, respectively; and

the first electrode is electrically connected to the input terminal.

7. The semiconductor device according to claim 6, wherein the second constant potential is lower than the first constant potential.

8. The semiconductor device according to claim 6, wherein the first to fifth transistors have the same conductivity type.

9. The semiconductor device according to claim 6, further comprising a first circuit which is capable of delaying a signal input thereto, wherein the gate of the fifth transistor is electrically connected to the input terminal through the first circuit.

10. The semiconductor device according to claim 6, further comprising a second circuit which is capable of delaying a signal input thereto, wherein the first electrode is electrically connected to the input terminal through the second circuit.

11. The semiconductor device according to claim 6, further comprising first and second circuits each of which is capable of delaying a signal input thereto,

wherein the gate of the fifth transistor is electrically connected to the input terminal through the first and second circuits,

wherein the first electrode is electrically connected to the input terminal through the second circuit, and

wherein the first electrode is electrically connected to the gate of the fifth transistor through the first circuit.

12. The semiconductor device according to claim 6, further comprising a first circuit which is capable of delaying a signal input thereto, wherein each of the gate of the second transistor and the gate of the fifth transistor is electrically connected to the input terminal through the first circuit.

13. The semiconductor device according to claim 6, further comprising a sixth transistor comprising a first terminal, a second terminal, and a gate,

wherein the gate of the third transistor is electrically connected to the second terminal of the fifth transistor through the sixth transistor, and

wherein the gate of the sixth transistor is electrically connected to the first wiring.

14. An electronic device comprising the semiconductor device according to claim 6.

25. The semiconductor device according to claim 6, wherein the second constant potential is lower than the first constant potential.

26. The semiconductor device according to claim 6, wherein the input terminal is configured to be applied with a first potential and a second potential which is different from the first potential.

15. A semiconductor device comprising:

a first wiring;

a second wiring configured to be applied with a first constant potential;

an output terminal;

first to fifth transistors each of which comprises a first terminal, a second terminal, and a gate; and

an inverter circuit,

wherein;

the first terminal, the second terminal, and the gate of the first transistor are electrically connected to the first wiring, the output terminal, and the second terminal of the fourth transistor, respectively;

the first terminal, the second terminal, and the gate of the second transistor are electrically connected to the second wiring, the output terminal, and the inverter circuit, respectively;

the first terminal, the second terminal, and the gate of the third transistor are electrically connected to the second wiring, the second terminal of the fourth transistor, and the inverter circuit, respectively;

the first terminal and the gate of the fourth transistor are electrically connected to each other; and

the first terminal and the second terminal of the fifth transistor are electrically connected to the second wiring and the second terminal of the fourth transistor, respectively.

16. The semiconductor device according to claim 15, wherein the first wiring is configured to be input a clock signal that oscillates between a high state and a low state.

17. The semiconductor device according to claim 15, wherein the first to fifth transistors have the same conductivity type.

18. The semiconductor device according to claim 15, further comprising a sixth transistor comprising a first terminal, a second terminal, and a gate, wherein the first terminal, the second terminal, and the gate of the sixth transistor are electrically connected to the second wiring, the output terminal, and the gate of the fifth transistor, respectively.

19. The semiconductor device according to claim 15, further comprising a third wiring and a sixth transistor which comprises a first terminal, a second terminal, and a gate,

wherein the first terminal, the second terminal, and the gate of the sixth transistor are electrically connected to the second wiring, the output terminal, and the third wiring, respectively,

wherein the first wiring is configured to be input a clock signal that oscillates between a high state and a low state, and

wherein the third wiring is configured to be input a signal whose phase is inverted with respect to the clock signal.

20. An electronic device comprising the semiconductor device according to claim 15.