Systems and methods for providing duty cycle correction
First Claim
Patent Images
1. A duty cycle module comprising:
- a first programmable delay to receive an input clock signal and output a first delayed clock signal;
an inverter to receive the input clock signal and output an inverted clock signal;
a second programmable delay to receive the inverted clock signal and output a second delayed clock signal;
a latch to combine the first delayed clock signal and the second delayed clock signal and generate a corrected clock signal;
a first timing circuit to measure a first pulse width of the corrected clock signal and output a first measurement;
a second timing circuit to measure a second pulse width of the corrected clock signal and output a second measurement;
a first comparator to output an UP control signal if the first measurement is greater than the second measurement at a desired time;
a second comparator to output a DOWN control signal if the second measurement is greater than the first measurement at the desired time; and
a duty cycle controller to receive at least one of the UP control signal and the DOWN control signal and adjust a setting of one of the first programmable delay and the second programmable delay based on the received at least one control signal in order to adjust a duty cycle of the corrected clock signal.
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Abstract
Systems and methods are disclosed including a duty cycle module having two timer circuits to measure pulse widths of a clock signal. Two comparators are used to generate control signals depending upon comparisons of the pulse width measurements. In response to the control signals, either the clock signal or an inverted clock signal may be programmably delayed such that combination of the clock signal and the inverted clock signal results in a corrected clock signal. Systems and methods are also disclosed for verifying operation of a duty cycle module.
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Citations
27 Claims
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1. A duty cycle module comprising:
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a first programmable delay to receive an input clock signal and output a first delayed clock signal; an inverter to receive the input clock signal and output an inverted clock signal; a second programmable delay to receive the inverted clock signal and output a second delayed clock signal; a latch to combine the first delayed clock signal and the second delayed clock signal and generate a corrected clock signal; a first timing circuit to measure a first pulse width of the corrected clock signal and output a first measurement; a second timing circuit to measure a second pulse width of the corrected clock signal and output a second measurement; a first comparator to output an UP control signal if the first measurement is greater than the second measurement at a desired time; a second comparator to output a DOWN control signal if the second measurement is greater than the first measurement at the desired time; and a duty cycle controller to receive at least one of the UP control signal and the DOWN control signal and adjust a setting of one of the first programmable delay and the second programmable delay based on the received at least one control signal in order to adjust a duty cycle of the corrected clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A duty cycle module comprising:
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a first programmable delay to delay an input clock signal and output a first delayed signal; a second programmable delay to delay an inverted input clock signal and output a second delayed signal; a latch to combine the first delayed clock signal and the second delayed clock signal and generate a corrected clock signal having a duty cycle; a duty cycle controller to receive information regarding characteristics of the duty cycle of the corrected clock signal and to adjust settings of the first programmable delay and the second programmable delay based on the information; and a test module to selectively override the duty cycle controller to apply a predetermined delay setting to one of the first programmable delay and the second programmable delay.
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11. A method for correcting a clock signal having a duty cycle, comprising:
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receiving a first clock signal having a rising edge as an input; inverting the first clock signal to generate a second clock signal having a rising edge; combining the first and second clock signals to generate a third clock signal having a rising edge corresponding to the rising edge of the first clock signal, a falling edge corresponding to the rising edge of the second clock signal and a duty cycle; generating a first timing signal corresponding to a first pulse width of the third clock signal; generating a second timing signal corresponding to a second pulse width of the third clock signal; generating a first control signal if the first timing signal is greater than the second timing signal at a first time; generating a second control signal indicating if the second timing signal is greater than the first timing signal at the first time; and correcting the duty cycle of the third clock signal by imparting a relative delay to one of the first clock signal and second clock signals based on at least one of the first and second control signals. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A method for verifying operation of a duty cycle module comprising:
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providing a duty cycle module including a first programmable delay to delay an input clock signal, a second programmable delay to delay an inverted input clock signal, and a duty cycle controller, wherein outputs of the first programmable delay and the second programmable delay are combined to generate a corrected clock signal having a duty cycle and wherein the duty cycle controller receives information regarding characteristics of the duty cycle of the corrected clock signal and adjusts settings of the first programmable delay and the second programmable delay based on the information; inputting a reference clock signal having a duty cycle of 50% as the input clock signal; selectively overriding the duty cycle controller to apply a predetermined delay setting to one of the first programmable delay and the second programmable delay; operating the duty cycle correction module to adjust the other programmable delay line until the corrected clock signal has an approximately 50% duty cycle; and verifying operation of the duty cycle module when the predetermined delay setting applied to the at least one of the first programmable delay and the second programmable delay corresponds to a setting for the other of the first programmable delay and the second programmable delay determined by the duty cycle controller. - View Dependent Claims (19, 20, 21)
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22. A duty cycle module comprising:
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means for delaying an input clock signal to output a first delayed signal; means for delaying an inverted signal of the input clock signal to output a second delayed signal; means for combining the first delayed signal and the second delayed signal to generate a corrected clock signal; a first timing means coupled to the corrected clock signal for measuring a first pulse width of the corrected clock signal and outputting a first measurement; a second timing means coupled to the corrected clock signal for measuring a second pulse width of the corrected clock signal and outputting a second measurement; a first comparator means, coupled to the first timing means and the second timing means, for outputting an UP control signal if the first measurement is greater than the second measurement at a desired time; a second comparator means, coupled to the first timing means and the second timing means, for outputting a DOWN control signal if the second measurement is greater than the first measurement at the desired time; and means for adjusting a setting of at least one of the means for delaying the input clock signal and the means for delaying the inverted signal based on at least one of the UP control signal and the DOWN control signal to adjust a duty cycle of the corrected clock signal. - View Dependent Claims (23, 24, 25, 26, 27)
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Specification