Signal isolators using micro-transformers

• US 8,736,343 B2
• Filed: 03/31/2011
• Issued: 05/27/2014
• Est. Priority Date: 04/30/2003
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Chen, Baoxing, Haigh, Geoffrey
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US13/077,324
• Publication Number:
  US 20110175642A1
• Time in Patent Office: 1,153 Days
• Field of Search: 326 21- 24, 327/510, 327/564, 375/219, 375/257, 375/258, 257/531
• US Class Current: 327/307
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 19/08 Transformers having magnetic bias, e.g. for handling pulses
• CPC Class Codes: H01F 2017/0093 Common mode choke coil
• CPC Class Codes: H01F 2019/085 Transformer for galvanic isolation
• CPC Class Codes: H01F 2038/143 for signals
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling

Abstract

A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Claims

1. A method for providing an isolated logic output signal, comprising:

in response to receiving an input data signal, generating a first edge detection signal indicating a rising edge of the received input data signal and a second edge detection signal indicating a falling edge of the received input data signal, the first edge detection signal being different from the second edge detection signal;

inputting the first and second edge detection signals to a primary winding of a transformer to transform the first and second edge detection signals from a first voltage to a second voltage, the first edge detection signal having a different pulse pattern than the second edge detection signal;

inputting the transformed edge detection signals from a secondary winding of the transformer to a first input of a D-type flip-flop and to an input of a nonretriggerable edge triggered mono-stable multivibrator;

outputting from the non-retriggerable edge triggered mono-stable multivibrator a logic signal to a second and third input of the D-type flip-flop, wherein the logic signal is representative of the pulse pattern of the first edge detection signal; and

in response to an output from the D-type flip-flop, generating an output signal.

2. The method of claim 1, further comprising:

applying the output signal from the D-type flip-flop to a first edge detection circuit and applying an inverted representation of the logic signal output from the non-retriggerable edge triggered mono-stable multivibrator to a second edge detection circuit.

3. The method of claim 2, further comprising:

applying the outputs of the first edge detection circuit and the second edge detection circuit to respective inputs on a pair of logic gates;

outputting a logic signal from one of the pair of logic gates; and

generating the isolated logic output signal in response to the respective one of the pair of logic gates that outputs the logic signal.

4. The method of claim 1, further comprising:

applying a logic signal output from the D-type flip-flop to a first input of a second logic circuit and applying an inverted representation of the logic signal output from the non-retriggerable edge triggered mono-stable multivibrator to a second input of the second logic circuit; and

generating the isolated logic output signal based on the applied logic signal to the first input of the second logic circuit.

5. A logic signal isolator comprising:

a first edge detector to detect a rising edge of a received input data

signal and generate a first edge detection signal;

a second edge detector to detect a falling edge of the received input data signal and generate a second edge detection signal, the first edge detection signal being different from the second edge detection signal;

a transformer having a primary winding and a secondary winding;

a transmitter circuit for driving the primary winding with the first edge detection signal and the second edge detection signal, the first edge detection signal having a different pulse pattern than the second edge detection signal;

a non-retriggerable edge triggered mono-stable multivibrator that responds to a transformed voltage present on the secondary winding of the transformer by generating a logic signal;

a D-type flip-flop having inputs for receiving the generated logic signal and having an output for outputting a first logic circuit signal; and

a flip-flop having inputs for receiving signals generated in response to the first logic circuit signal and an output for outputting an isolated logic signal.

6. The logic signal isolator of claim 5, further comprising:

a first edge detection circuit connected between the output of the D-type flip-flop and a first input of the flip-flop; and

a second edge detection circuit connected between an output of the non-retriggerable edge triggered mono-stable multivibrator via an inverter and a second input to the flip-flop.

7. A method for providing an isolated logic output signal, comprising:

in response to receiving an input data signal, generating an edge detection signal indicating a rising or falling edge of the received input data signal;

transforming the edge detection signal from a first voltage to a second voltage;

inputting the transformed edge detection signal to a first input of a first logic circuit and to an input of a signal generator;

outputting from the signal generator a logic signal to a second and third input of the first logic circuit, wherein the logic signal is representative of a pulse pattern of the edge detection signal; and

in response to an output from the first logic signal, generating an isolated logic output signal.

8. The method of claim 7, further comprising:

in response to receiving the transformed edge detection signal at the first input of the first logic signal, outputting from the first logic circuit a logic signal, wherein the first logic circuit is a flip-flop circuit.

9. The method of claim 8, further comprising:

applying the logic signal output from the first logic circuit to a first edge detection circuit and applying an inverted representation of the logic signal output from the signal generator to a second edge detection circuit.

10. The method of claim 9, further comprising:

applying the outputs of the first edge detection circuit and the second edge detection circuit to respective inputs on a pair of logic gates;

outputting a logic signal from one of the pair of logic gates; and

generating the isolated logic output signal in response to the respective one of the pair of logic gates that outputs the logic signal.

11. The method of claim 7, further comprising:

applying a logic signal output from the first logic circuit to a first input of a second logic circuit and applying an inverted representation of the logic signal output from the signal generator to a second input of the second logic circuit; and

generating the isolated logic output signal based on the applied logic signal to the first input of the second logic circuit.

12. The method of claim 7, wherein the transforming comprises:

applying the edge detection signal at the first voltage to a primary winding of a transformer, and outputting from a second winding of the transformer the transformed edge detection signal at the second voltage.

13. A logic signal isolator comprising:

a transformer having a primary winding and a secondary winding;

a transmitter circuit for driving the primary winding in response to a received input logic signal;

a signal generating circuit comprising a nonretriggerable edge triggered mono-stable multivibrator that responds to a transformed voltage present on the secondary winding of the transformer by generating a logic signal;

a first logic circuit having inputs for receiving the generated logic signal and the transformed voltage present on the secondary winding of the transformer, and having an output for outputting a first logic circuit signal; and

a second logic circuit having inputs for receiving signals generated in response to the first logic circuit signal and an output for outputting an isolated logic signal.

14. The logic signal isolator of claim 13, further comprising:

a first edge detection circuit connected between the output of the first logic circuit and a first input of the second logic circuit; and

a second edge detection circuit connected between an output of the signal generating circuit via an inverter and a second input to the second logic circuit.