Semiconductor device having transistors each of which includes an oxide semiconductor

• US 8,736,371 B2
• Filed: 05/10/2012
• Issued: 05/27/2014
• Est. Priority Date: 05/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohnuki, Tatsuya
• Primary Examiner(s): Mottola, Steven J
• Application Number:
  US13/468,117
• Publication Number:
  US 20120286871A1
• Time in Patent Office: 747 Days
• Field of Search: 330/255, 330/264, 330/267
• US Class Current: 330/255
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 2203/45674 the LC comprising one current mirror
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence

Abstract

To provide a semiconductor device with low power consumption, in a semiconductor device including a differential amplifier to which an input potential and a reference potential are input, a gain stage, and an output stage from which an output potential is output, a potential supplied from the gain stage can be held constant by providing the output stage with a transistor with low leakage current in an off state. As the transistor with low leakage current in an off state, a transistor including an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer is used.

Claims

1. A semiconductor device comprising:

a first input terminal to which an input potential is input;

a second input terminal to which a reference potential is input;

a first output terminal from which an output potential is output;

a differential amplifier electrically connected to the first input terminal and the second input terminal; and

a gain stage comprising a first transistor, a second transistor, a third transistor, and a fourth transistor, and electrically connected to the first output terminal;

wherein the differential amplifier is electrically connected to a first power supply potential line and a second power supply potential line,

wherein a potential of the first power supply potential line is higher than that of the second power supply potential line,

wherein a first terminal of the first transistor is electrically connected to a second output terminal of the differential amplifier,

wherein a second terminal of the first transistor is electrically connected to a gate of the third transistor,

wherein a first terminal of the second transistor is electrically connected to the second input terminal,

wherein a second terminal of the second transistor is electrically connected to a gate of the fourth transistor,

wherein a first terminal of the third transistor is electrically connected to the first power supply potential line,

wherein a second terminal of the third transistor and a first terminal of the fourth transistor are electrically connected to the first output terminal,

wherein a second terminal of the fourth transistor is electrically connected to the second power supply potential line, and

wherein the first transistor and the second transistor are each a transistor whose leakage current in an off state per micrometer of a channel width is lower than or equal to 1×

10<sup>−

17</sup> A.

2. A semiconductor device comprising:

a first input terminal to which an input potential is input;

a second input terminal to which a reference potential is input;

a first output terminal from which an output potential is output;

a differential amplifier electrically connected to the first input terminal and the second input terminal;

an output stage comprising a first transistor, a second transistor, a third transistor, and a fourth transistor, and electrically connected to the first output terminal; and

a gain stage provided between the differential amplifier and the output stage and electrically connected to the differential amplifier and the output stage,

wherein the differential amplifier and the gain stage are electrically connected to a first power supply potential line and a second power supply potential line,

wherein a potential of the first power supply potential line is higher than that of the second power supply potential line,

wherein a first terminal of the first transistor is electrically connected to a second output terminal of the gain stage,

wherein a second terminal of the first transistor is electrically connected to a gate of the third transistor,

wherein a first terminal of the second transistor is electrically connected a third output terminal of the gain stage,

wherein a second terminal of the second transistor is electrically connected to a gate of the fourth transistor,

wherein a first terminal of the third transistor is electrically connected to the first power supply potential line,

wherein a second terminal of the third transistor and a first terminal of the fourth transistor are electrically connected to the first output terminal,

wherein a second terminal of the fourth transistor is electrically connected to the second power supply potential line,

wherein the first transistor and the second transistor are each a transistor whose leakage current in an off state per micrometer of a channel width is lower than or equal to 1×

10<sup>−

17</sup> A, and

wherein the same potential is supplied to gates of the first transistor and the second transistor.

3. The semiconductor device according to claim 1, wherein the first transistor and the second transistor each include an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer.

4. The semiconductor device according to claim 2, wherein the first transistor and the second transistor each include an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer.

5. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor;

an eighth transistor; and

a ninth transistor,

wherein a first terminal of the first transistor and a first terminal of the second transistor are electrically connected to a first power supply potential line,

wherein a second terminal of the first transistor is electrically connected to a gate of the first transistor, a gate of the second transistor, and a first terminal of the third transistor,

wherein a second terminal of the second transistor is electrically connected to a first terminal of the fourth transistor,

wherein a second terminal of the third transistor and a second terminal of the fourth transistor are electrically connected to a first terminal of the fifth transistor,

wherein a second terminal of the fifth transistor is electrically connected to a second power supply potential line,

wherein a potential of the first power supply potential line is higher than that of the second power supply potential line,

wherein a first terminal of the sixth transistor is electrically connected to the first power supply potential line,

wherein a first terminal of the seventh transistor is electrically connected to the second terminal of the second transistor and the first terminal of the fourth transistor,

wherein a second terminal of the seventh transistor is electrically connected to a gate of the sixth transistor,

wherein a first terminal of the eighth transistor is electrically connected to a gate of the fifth transistor,

wherein a second terminal of the eighth transistor is electrically connected to a gate of the ninth transistor,

wherein a first terminal of the ninth transistor is electrically connected to the second terminal of the fifth transistor and the second power supply potential line,

wherein a gate of the fourth transistor is electrically connected to a first input terminal to which an input potential is input,

wherein a gate of the third transistor, a second terminal of the sixth transistor, and a second terminal of the ninth transistor are electrically connected to an output terminal,

wherein the gate of the fifth transistor is electrically connected to a second input terminal to which a reference potential is input,

wherein the first transistor, the second transistor, and the sixth transistor are p-channel transistors,

wherein the third transistor, the fourth transistor, the fifth transistor, and the ninth transistor are n-channel transistors, and

wherein the seventh transistor and the eighth transistor are each a transistor whose leakage current in an off state per micrometer of a channel width is lower than or equal to 1×

10<sup>—

17</sup> A.

6. The semiconductor device according to claim 5, wherein the seventh transistor and the eighth transistor each include an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer.

7. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor;

an eighth transistor;

a ninth transistor;

a tenth transistor;

an eleventh transistor;

a twelfth transistor;

a thirteenth transistor; and

a capacitor,

wherein a first terminal of the first transistor and a first terminal of the second transistor are electrically connected to a first power supply potential line,

wherein a second terminal of the first transistor is electrically connected to a gate of the first transistor, a gate of the second transistor, and a first terminal of the third transistor,

wherein a second terminal of the second transistor is electrically connected to a first terminal of the fourth transistor,

wherein a second terminal of the third transistor and a second terminal of the fourth transistor are electrically connected to a first terminal of the fifth transistor,

wherein a second terminal of the fifth transistor is electrically connected to a second power supply potential line,

wherein a potential of the first power supply potential line is higher than that of the second power supply potential line,

wherein a first terminal of the sixth transistor is electrically connected to the first power supply potential line,

wherein the second terminal of the second transistor and the first terminal of the fourth transistor are electrically connected to a gate of the sixth transistor and one electrode of the capacitor,

wherein a second terminal of the sixth transistor and the other electrode of the capacitor are electrically connected to a first terminal of the seventh transistor and a gate of the seventh transistor,

wherein a second terminal of the seventh transistor is electrically connected to a first terminal of the eighth transistor,

wherein a second terminal of the eighth transistor is electrically connected to a gate of the eighth transistor and a first terminal of the ninth transistor,

wherein a second terminal of the ninth transistor is electrically connected to the second power supply potential line,

wherein a first terminal of the tenth transistor is electrically connected to the first power supply potential line,

wherein a first terminal of the eleventh transistor is electrically connected to the gate of the seventh transistor,

wherein a gate of the tenth transistor is electrically connected to a second terminal of the eleventh transistor,

wherein a first terminal of the twelfth transistor is electrically connected to the gate of the eighth transistor,

wherein a second terminal of the twelfth transistor is electrically connected to a gate of the thirteenth transistor,

wherein a second terminal of the tenth transistor is electrically connected to a first terminal of the thirteenth transistor,

wherein a second terminal of the thirteenth transistor is electrically connected to the second power supply potential line,

wherein a gate of the fourth transistor is electrically connected to a first input terminal to which an input potential is input,

wherein a gate of the third transistor, the second terminal of the tenth transistor, and the first terminal of the thirteenth transistor are electrically connected to an output terminal from which an output potential is output,

wherein a gate of the fifth transistor and a gate of the ninth transistor are electrically connected to a second input terminal to which a reference potential is input,

wherein the first transistor, the second transistor, the sixth transistor, the eighth transistor, and the thirteenth transistor are p-channel transistors,

wherein the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, the ninth transistor, and the tenth transistor are n-channel transistors, and

wherein the eleventh transistor and the twelfth transistor are each a transistor whose leakage current in an off state per micrometer of a channel width is lower than or equal to 1×

10<sup>−

17</sup> A.

8. The semiconductor device according to claim 7, wherein the eleventh transistor and the twelfth transistor each include an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer.

9. The semiconductor device according to claim 1, wherein the same potential is supplied to gates of the first transistor and the second transistor.

10. The semiconductor device according to claim 1,

wherein a channel formation region of each of the first transistor and the second transistor include an oxide semiconductor layer, and

wherein a carrier concentration in the oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

11. The semiconductor device according to claim 1,

wherein a channel formation region of each of the first transistor and the second transistor include an oxide semiconductor layer, and

wherein an energy gap of the oxide semiconductor layer is higher than 2.5 eV.

12. The semiconductor device according to claim 2,

wherein a channel formation region of each of the first transistor and the second transistor include an oxide semiconductor layer, and

wherein a carrier concentration in the oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

13. The semiconductor device according to claim 2,

wherein a channel formation region of each of the first transistor and the second transistor include an oxide semiconductor layer, and

wherein an energy gap of the oxide semiconductor layer is higher than 2.5 eV.

14. The semiconductor device according to claim 5, wherein the same potential is supplied to gates of the seventh transistor and the eighth transistor.

15. The semiconductor device according to claim 5,

wherein a channel formation region of each of the seventh transistor and the eighth transistor include an oxide semiconductor layer, and

wherein a carrier concentration in the oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

16. The semiconductor device according to claim 5,

wherein a channel formation region of each of the first transistor and the second transistor include an oxide semiconductor layer, and

wherein an energy gap of the oxide semiconductor layer is higher than 2.5 eV.

17. The semiconductor device according to claim 7, wherein the same potential is supplied to gates of the eleventh transistor and the twelfth transistor.

18. The semiconductor device according to claim 7,

wherein a channel formation region of each of the eleventh transistor and the twelfth transistor include an oxide semiconductor layer, and

wherein a carrier concentration in the oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

19. The semiconductor device according to claim 7,

wherein a channel formation region of each of the eleventh transistor and the twelfth transistor include an oxide semiconductor layer, and

wherein an energy gap of the oxide semiconductor layer is higher than 2.5 eV.