Systems and methods for providing a shared buffer in a multiple FIFO environment

• US 8,736,627 B2
• Filed: 12/19/2006
• Issued: 05/27/2014
• Est. Priority Date: 12/19/2006
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Brothers, John
• Primary Examiner(s): Merouan, Abderrahim
• Application Number:
  US11/612,573
• Publication Number:
  US 20080143733A1
• Time in Patent Office: 2,716 Days
• Field of Search: 345501- 54, 345/558, 345/531, 345/522, 345/506, 345/503, 345/556, 345/536, 345/422, 345/541, 712 1-248, 711/128, 711/133, 711/129
• US Class Current: 345/541
• CPC Class Codes: G06T 1/60 Memory management

Abstract

Provided are methods and systems for reducing memory bandwidth usage in a common buffer, multiple FIFO computing environment. The multiple FIFO'"'"'s are arranged in coordination with serial processing units, such as in a pipeline processing environment. The multiple FIFO'"'"'s contain pointers to entry addresses in a common buffer. Each subsequent FIFO receives only pointers that correspond to data that has not been rejected by the corresponding processing unit. Rejected pointers are moved to a free list for reallocation to later data.

Claims

1. A system for sharing a buffer in a computer graphics processing environment, comprising:

a shared buffer configured to receive and store a plurality of attribute values corresponding to a plurality of graphics data values;

a plurality of data processing components, organized serially in a computer graphics pipeline, configured to process the plurality of graphics data values;

a plurality of pointer arrays organized serially along a path that is parallel to the computer graphics pipeline, the pointer arrays configured to maintain a plurality of pointers that point to entry addresses of the shared buffer, the entry addresses corresponding to data storage fields of the shared buffer for storing the plurality of attribute values, wherein the plurality of pointers is forwarded along the path parallel to the computer graphics pipeline; and

a buffer mask configured to identify an availability of at least one entry address of the shared buffer, the availability indicating whether or not the data storage field corresponding to the respective entry address is free to receive new attribute values, allowing graphics data values stored in the data storage field corresponding to the respective entry address to be overwritten.

2. The system of claim 1, wherein the buffer mask includes a plurality of bits corresponding to a plurality of addresses in the shared buffer.

3. The system of claim 1, wherein one of the plurality of data processing components comprises an attribute setup unit, configured to generate the plurality of attribute values, and another of the plurality of data processing components comprises a Z test unit.

4. The system of claim 3, wherein one of the plurality of pointer arrays comprises a first pointer array logically configured between the attribute setup unit and the Z test unit.

5. The system of claim 4, further comprising:

a first triangle; and

a first bit, corresponding to a first shared buffer memory address, wherein if the first triangle is rejected by the Z test unit then the first bit is written to the buffer mask.

6. The system of claim 5, further comprising a first pointer of the plurality of pointers, wherein the first pointer is discarded from the first pointer array and wherein the first pointer corresponds to the first triangle, if the first triangle is rejected by the Z test unit.

7. The system of claim 1, wherein each of the plurality of pointer arrays corresponds to two of the plurality of data processing components.

8. The system of claim 7, further comprising:

a triangle; and

an attribute delta data pointer, corresponding to the triangle delta data of the triangle;

wherein if the triangle is rejected by one of the plurality of data processing components then the attribute delta data pointer is discarded by the one of the plurality of pointer arrays that corresponds to the one of the plurality of data processing units.

9. The system of claim 8, further comprising a state data pointer, corresponding to state data of the triangle, wherein the state data pointer is transferred to an adjacent one of the plurality of pointer arrays.

10. The system of claim 1, wherein each of the plurality of pointer arrays comprises capacity to maintain a number of pointers equal to a number of addresses in the shared buffer.

11. The system of claim 1, wherein one of the data processing components comprises an interpolation unit.

12. The system of claim 11, wherein one of the plurality of pointer arrays is configured to compensate for texture read latency and corresponds to the interpolation unit and wherein each of the plurality of pointer arrays comprises a first-in-first-out buffer.

13. The system of claim 1, wherein a portion of the plurality of attribute values comprises triangle delta data.

14. The system of claim 13, wherein another portion of the plurality of attribute values comprises state data.

15. The system of claim 1, wherein the overwritten graphics data values are data rejected by the computer graphics pipeline.

16. The system of claim 15, wherein, by overwriting the graphics data values rejected by the computer graphics pipeline, the buffer mask eliminates the continued processing of the rejected graphics data values.