Methods and systems for reducing power consumption in dual modulation displays

• US 8,736,643 B2
• Filed: 02/15/2011
• Issued: 05/27/2014
• Est. Priority Date: 02/22/2010
• Status: Active Grant

• Current Assignee: Dolby Laboratories Licensing Corporation (Dolby Laboratories Incorporated)
• Original Assignee: Dolby Laboratories Licensing Corporation (Dolby Laboratories Incorporated)
• Inventors: Messmer, Neil W.
• Primary Examiner(s): Chow, Van
• Application Number:
  US13/578,251
• Publication Number:
  US 20120306943A1
• Time in Patent Office: 1,197 Days
• Field of Search: 345/690
• US Class Current: 345/690
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0646 Modulation of illumination source brightness and image signal correlated to each other
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/16 Calculation or use of calculated indices related to luminance levels in display data
• CPC Class Codes: G09G 3/3426 the different display panel areas being distributed in two dimensions, e.g. matrix

Abstract

A control system for a dual modulation display comprises an input configured to receive image data specifying a desired image at an initial resolution, a downsampler configured to downsample the image data into a plurality of downsample blocks and obtain one or more image values for each downsample block, a backlight processing pipeline which determines driving levels for light emitters based on the image values, a lightfield simulator which receives data about the driving levels and generates a backlight illumination pattern, a front modulator processing pipeline which receives the image data and the backlight illumination pattern and determines control levels for light transmission elements of the front modulator, and, an image value adjuster which receives the image values and reduces image values of downsample blocks which meet adjustment criteria before providing the image values to the backlight processing pipeline.

Claims

1. A control system for a display comprising a backlight having a plurality of individually controllable light emitters configured to project light onto a front modulator having a plurality of individually controllable light transmission elements, the control system comprising:

an input configured to receive image data specifying a desired image at an initial resolution;

a downsampler configured to downsample the image data into a plurality of downsample blocks at a downsample spatial resolution lower than the initial spatial resolution and obtain one or more image values for each downsample block;

wherein the image values comprise a peak value and an average value for each downsample block;

an image value adjuster configured to receive the image values for the downsample blocks from the downsampler and reduce the average values of the image values for each downsample block which meets adjustment criteria before providing the reduced average values of the image values to the backlight processing pipeline;

a backlight processing pipeline configured to determine driving levels for the light emitters of the backlight based on the reduced average values of the image values output from the image value adjuster, the reduced average values of the image values resulting in a reduction in the power consumption of the light emitters of the backlight;

a lightfield simulator configured to receive backlight driving data about the driving levels and to transform the backlight driving data into a backlight illumination pattern; and

,

a front modulator processing pipeline configured to receive the image data from the input and the backlight illumination pattern from the lightfield simulator and to determine control levels for the light transmission elements of the front modulator;

wherein the adjustment criteria are met when the peak value is below an upper watermark and the average value is above a lower watermark;

wherein image values and upper and lower watermarks are represented using N bits, where N is a positive integer;

wherein the upper watermark has a value of 2^N-1−

1, and the lower watermark has a value of 2^M-1, where M is a positive integer less than N−

1.

2. A control system according to claim 1 wherein the image values comprise a plurality of peak values and a plurality of average values for each downsample block.

3. A control system according to claim 1 comprising an image filtering element connected to filter the image values output by the image value adjuster.

4. A control system according to claim 1 wherein the image value adjuster generates the reduced average value by dividing the average value by 2ⁿ, where n is a positive integer.

5. A control system according to claim 1 wherein the image value adjuster generates the reduced average value by reducing the average value logarithmically.

6. A control system according to claim 1 wherein the image value adjuster generates the reduced average value by calculating a scaled average value based on a ratio of the peak value to the upper watermark.

7. A control system according to claim 6 wherein the image value adjuster adds an offset to the scaled average value.

8. A control system according to claim 1 wherein the image value adjuster is configured to compare the reduced average value to a minimum average threshold and provide an original average value to the backlight processing pipeline when the reduced average value is below the minimum average threshold.

9. A control system according to claim 8 wherein the image value adjuster is configured to generate the reduced average value by iteratively reducing the average value until a current reduced average value is below the minimum average threshold and selecting a previous reduced average value for providing to the backlight processing pipeline.