Memory device and semiconductor device

• US 8,737,109 B2
• Filed: 08/23/2011
• Issued: 05/27/2014
• Est. Priority Date: 08/27/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US13/215,489
• Publication Number:
  US 20120051118A1
• Time in Patent Office: 1,008 Days
• Field of Search: 365/149, 365/51, 365/63, 365/72
• US Class Current: 365/72
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a switching element for controlling supply, storage, and release of electrical charge in the memory element. The transistor includes a second gate electrode for controlling the threshold voltage in addition to a normal gate electrode. Further, the off-state current of the transistor is extremely low because an active layer thereof includes an oxide semiconductor. In the memory device, data is stored not by injection of electrical charge to a floating gate surrounded by an insulating film at high voltage but by control of the amount of electrical charge of the memory element through the transistor whose off-state current is extremely low.

Claims

1. A memory device comprising:

a transistor comprising an oxide semiconductor layer, a first gate electrode, and a second gate electrode; and

a memory element electrically connected to the oxide semiconductor layer,

wherein a lowest potential of the first gate electrode for a writing period, a reading period and a retention period is configured to be higher than or equal to a first potential,

wherein a highest potential of the second gate electrode for the writing period, the reading period and the retention period is configured to be lower than or equal to the first potential to control a threshold voltage of the transistor, and

wherein the oxide semiconductor layer is interposed between the first gate electrode and the second gate electrode.

2. The memory device according to claim 1,

wherein the memory element is a capacitor.

7. The memory device according to any one of claims 1, 3, 5, and 6, wherein the oxide semiconductor layer includes an In—

Ga—

Zn-based oxide semiconductor.

8. The memory device according to any one of claims 1, 3, 5, and 6, wherein concentration of hydrogen in the oxide semiconductor layer is 5×

10¹⁹/cm³ or lower.

9. A semiconductor device comprising the memory device according to any one of claims 1, 3, 5, and 6.

10. The memory device according to claim 1 or 5, wherein the memory element includes a capacitor.

17. The memory device according to any one of claims 1, 3, 5, and 6, further comprising a first insulating film and a second insulating film,

wherein the first insulating film is interposed between the first gate electrode and the oxide semiconductor layer, and

wherein the second insulating film is interposed between the oxide semiconductor layer and the second gate electrode.

18. The memory device according to claim 17, wherein the second gate electrode is located over the first gate electrode.

3. A memory device comprising:

a first transistor comprising an oxide semiconductor layer, a first gate electrode, and a second gate electrode; and

a second transistor comprising a third gate electrode electrically connected to the oxide semiconductor layer,

wherein a lowest potential of the first gate electrode for a writing period, a reading period and a retention period is configured to be higher than or equal to a first potential,

wherein a highest potential of the second gate electrode for the writing period, the reading period and the retention period is configured to be lower than or equal to the first potential to control a threshold voltage of the first transistor, and

wherein the oxide semiconductor layer is interposed between the first gate electrode and the second gate electrode.

4. The memory device according to claim 3, further comprising a capacitor electrically connected to the first gate electrode.

11. The memory device according to claim 3 or 6, further comprising a first capacitor electrically connected to the third gate electrode.

5. A memory device comprising:

a memory cell comprising a first transistor and a memory element; and

a driver circuit comprising a second transistor,

wherein the first transistor comprises a first gate electrode, a second gate electrode, and an oxide semiconductor layer interposed between the first gate electrode and the second gate electrode,

wherein the second transistor comprises a third gate electrode, a first electrode, and a second electrode,

wherein the third gate electrode is electrically connected to the first electrode and the second gate electrode,

wherein a lowest potential of the first gate electrode for a writing period, a reading period and a retention period is configured to be higher than or equal to a first potential, and

wherein a highest potential of the second gate electrode for the writing period, the reading period and the retention period is configured to be lower than or equal to the first potential to control a threshold voltage of the first transistor.

12. The memory device according to claim 5,

wherein the second transistor further comprises a semiconductor layer and a fourth gate electrode electrically connected to the third gate electrode, and

wherein the semiconductor layer is interposed between the third gate electrode and the fourth gate electrode.

13. The memory device according to claim 12, wherein the semiconductor layer includes an oxide semiconductor.

16. The memory device according to claim 5 or 6,

wherein the driver circuit further comprises a second capacitor electrically connected to the second gate electrode.

19. The memory device according to claim 5 or 6, wherein, when the threshold voltage of the first transistor is changed by controlling the potential of the second gate electrode, a potential of the second electrode is lower than that of the second gate electrode.

6. A memory device comprising:

a memory cell comprising a first transistor and a second transistor; and

a driver circuit comprising a third transistor,

wherein the first transistor comprises a first gate electrode, a second gate electrode, and an oxide semiconductor layer interposed between the first gate electrode and the second gate electrode,

wherein the second transistor comprises a third gate electrode electrically connected to the oxide semiconductor layer,

wherein the third transistor comprises a fourth gate electrode, a first electrode, and a second electrode,

wherein the fourth gate electrode is electrically connected to the first electrode and the second gate electrode,

wherein a lowest potential of the first gate electrode for a writing period, a reading period and a retention period is configured to be higher than or equal to a first potential, and

wherein a highest potential of the second gate electrode for the writing period, the reading period and the retention period is configured to be lower than or equal to the first potential to control a threshold voltage of the first transistor.

14. The memory device according to claim 6,

wherein the third transistor further comprises a semiconductor layer and a fifth gate electrode electrically connected to the fourth gate electrode, and

wherein the semiconductor layer is interposed between the fourth gate electrode and the fifth gate electrode.

15. The memory device according to claim 14, wherein the semiconductor layer includes an oxide semiconductor.

20. A semiconductor device comprising:

a first wiring;

a second wiring;

a first transistor comprising a first oxide semiconductor layer, a first gate electrode, and a second gate electrode; and

a second transistor comprising a second oxide semiconductor layer and a third gate electrode,

wherein the first oxide semiconductor layer is interposed between the first gate electrode and the second gate electrode,

wherein the second oxide semiconductor layer is electrically connected to the second wiring,

wherein the first gate electrode and the second electrode are electrically connected to the first oxide semiconductor layer,

wherein the third gate electrode is electrically connected to the second gate electrode through the first wiring, and

wherein a potential of the first wiring is configured to be constant and always lower than a potential of the second wiring.

23. The semiconductor device according to any one of claims 20-22, wherein the first transistor is included in a word line driver circuit.

24. The semiconductor device according to claim 20 or 21, wherein the second transistor is included in a memory cell.

26. The semiconductor device according to any one of claims 20-22, further comprising a capacitor electrically connected to the first wiring.

21. A semiconductor device comprising:

a first wiring;

a second wiring;

a first transistor comprising a first oxide semiconductor layer, a first gate electrode, and a second gate electrode; and

a second transistor comprising a second oxide semiconductor layer and a third gate electrode,

wherein the first oxide semiconductor layer is interposed between the first gate electrode and the second gate electrode,

wherein the second oxide semiconductor layer is electrically connected to the second wiring,

wherein the first gate electrode and the second electrode are electrically connected to the first oxide semiconductor layer,

wherein the third gate electrode is electrically connected to the second gate electrode through the first wiring, and

wherein a potential of the second gate electrode is configured to be constant and always lower than a potential of the second wiring.

22. A semiconductor device comprising:

a first wiring;

a second wiring;

a first transistor comprising a first oxide semiconductor layer, a first gate electrode, and a second gate electrode; and

a plurality of second transistors each comprising a second oxide semiconductor layer and a third gate electrode,

wherein the first oxide semiconductor layer is interposed between the first gate electrode and the second gate electrode,

wherein the second oxide semiconductor layer is electrically connected to the second wiring,

wherein the first gate electrode and the second electrode are electrically connected to the first oxide semiconductor layer,

wherein the third gate electrode is electrically connected to the second gate electrode through the first wiring, and

wherein a potential of the first wiring is configured to be constant and always lower than a potential of the second wiring.

25. The semiconductor device according to claim 22, wherein the plurality of second transistors is included in a cell array.