Nonvolatile semiconductor storage device

• US 8,737,134 B2
• Filed: 03/12/2012
• Issued: 05/27/2014
• Est. Priority Date: 09/02/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shiino, Yasuhiro, Takahashi, Eietsu, Takeuchi, Yuji
• Primary Examiner(s): Dinh, Son
• Assistant Examiner(s): NGUYEN, NAM THANH
• Application Number:
  US13/417,719
• Publication Number:
  US 20130058170A1
• Time in Patent Office: 806 Days
• Field of Search: 365/185.2, 365/185.29, 365/185.23
• US Class Current: 365/185.2
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells

Abstract

A nonvolatile semiconductor storage device according to an embodiment includes a drive circuit. A voltage applied to a dummy wire connected to a first dummy cell adjacent to a memory string is defined as a first dummy wire voltage, a voltage applied to a selection wire connected to a first memory cell adjacent to the first dummy cell is defined as a first selection wire voltage, and a voltage applied to a selection wire connected to a second memory cell adjacent to the first memory cell is defined as a second selection wire voltage. When the second selection wire voltage is lower than the first dummy wire voltage in an erase operation, the drive circuit controls voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.

Claims

1. A nonvolatile semiconductor storage device comprising:

a cell array including a cell unit, a selection wire and a dummy wire, the cell unit including a memory string in which a plurality of memory cells for storing data are connected in series and one or more dummy cells being provided at one end of the memory string, the selection wire connecting to each of the memory cells, and the dummy wire connecting to each of the dummy cells; and

a drive circuit applying voltages to the selection wire and the dummy wire during erase operation for erasing data in the memory cells,

the dummy cell adjacent to the memory string being defined as a first dummy cell, the memory cell adjacent to the first dummy cell being defined as a first memory cell, the memory cell adjacent to the first memory cell being defined as a second memory cell, a voltage applied to the dummy wire connected to the first dummy cell being defined as a first dummy wire voltage, a voltage applied to the selection wire connected to the first memory cell being defined as a first selection wire voltage, and a voltage applied to the selection wire connected to the second memory cell being defined as a second selection wire voltage, and

when the second selection wire voltage is lower than the first dummy wire voltage in the erase operation, the drive circuit controlling the voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.

2. The nonvolatile semiconductor storage device according to claim 1, wherein

the drive circuit executes erase verification operation to confirm erasing of data in the memory cells, and

when the second selection wire voltage is lower than the first dummy wire voltage in the erase verification operation, the drive circuit controls the voltages so that the difference between the first dummy wire voltage and the second selection wire voltage is less than the difference between the first dummy wire voltage and the first selection wire voltage.

3. The nonvolatile semiconductor storage device according to claim 2, wherein the memory cells of the memory string that are connected to odd-numbered points or even-numbered points are adopted as targets of the erase verification operation.

4. The nonvolatile semiconductor storage device according to claim 1, wherein the cell array includes two or more dummy cells which are provided at one end of the memory string and are connected in series.

5. The nonvolatile semiconductor storage device according to claim 4, wherein

a voltage applied to the dummy wire connected to the dummy cell adjacent to the first dummy cell is defined as a second dummy wire voltage, and

the drive circuit controls the voltages so that the first dummy wire voltage is lower than the second dummy wire voltage in the erase operation.

6. The nonvolatile semiconductor storage device according to claim 3, wherein

a memory cell of the memory string connected at one of an odd-numbered point and an even-numbered point is defined as a first target cell, and a memory cell of the memory string connected at the other of the odd-numbered point and the even-numbered point is defined as a second target cell, and

the drive circuit repeatedly executes the erase operation and the erase verification operation for the first target cell until the erase verification operation is passed, and thereafter repeatedly executes the erase verification operation for the second target cell along with the erase operation until the erase verification operation is passed.

7. The nonvolatile semiconductor storage device according to claim 1, wherein

the memory string includes the first memory cell, the second memory cell, and a third memory cell being the other memory cell,

a voltage applied to the selection wire connected to the third memory cell is defined as a third selection wire voltage, and

the drive circuit controls the voltages so that the third selection wire voltage is the same as the second wire selection voltage in the erase operation.

18. The nonvolatile semiconductor storage device according to claim 1, wherein

each of the memory cells is configured to have a threshold voltage indicative of stored data, and

the drive circuit causes the first dummy cell to attain a threshold voltage close to the threshold voltage corresponding to an erased state of the memory cell during the erase operation.

8. A nonvolatile semiconductor storage device comprising:

a cell array including a cell unit, a selection wire and a dummy wire, the cell unit including a memory string in which a plurality of memory cells for storing data are connected in series and one or more dummy cells being provided at one end of the memory string, the selection wire connecting to each of the memory cells, and the dummy wire connecting to each of the dummy cells; and

a drive circuit for applying voltages to the selection wire and the dummy wire during erase verification operation for confirming erasing of data in the memory cells,

the dummy cell adjacent to the memory string being defined as a first dummy cell, the memory cell adjacent to the first dummy cell being defined as a first memory cell, the memory cell adjacent to the first memory cell being defined as a second memory cell, a voltage applied to the dummy wire connected to the first dummy cell being defined as a first dummy wire voltage, a voltage applied to the selection wire connected to the first memory cell being defined as a first selection wire voltage, and a voltage applied to the selection wire connected to the second memory cell being defined as a second selection wire voltage, and

when the second selection wire voltage is lower than the first dummy wire voltage in the erase verification operation, the drive circuit controlling the voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.

9. The nonvolatile semiconductor storage device according to claim 8, wherein the memory cells of the memory string that are connected to odd-numbered points or even-numbered points are adopted as targets of the erase verification operation.

10. The nonvolatile semiconductor storage device according to claim 8, wherein the cell array includes two or more dummy cells which are provided at one end of the memory string and are connected in series.

11. The nonvolatile semiconductor storage device according to claim 10, wherein

a voltage applied to the dummy wire connected to the dummy cell adjacent to the first dummy cell is defined as a second dummy wire voltage, and

the drive circuit controls the voltages the first dummy wire voltage is lower than the second dummy wire voltage in the erase verification operation.

12. The nonvolatile semiconductor storage device according to claim 9, wherein

a memory cell of the memory string connected at one of an odd-numbered point and an even-numbered point is defined as a first target cell, and a memory cell of the memory string connected at the other of the odd-numbered point and the even-numbered point is defined as a second target cell, and

the drive circuit repeatedly executes the erase operation for erasing the data in the memory cells and the erase verification operation for the first target cell until the erase verification operation is passed, and thereafter repeatedly executes the erase verification operation for the second target cell along with the erase operation until the erase verification operation is passed.

13. The nonvolatile semiconductor storage device according to claim 8, wherein

the memory string includes the first memory cell, the second memory cell, and a third memory cell being the other memory cell,

a voltage applied to the selection wire connected to the third memory cell is defined as a third selection wire voltage, and

the drive circuit controls the voltages so that the third selection wire voltage is the same as the second wire selection voltage in the erase verification operation.

14. A nonvolatile semiconductor storage device comprising:

a cell array including a cell unit, a selection wire and a gate wire, the cell unit including a memory string in which a plurality of memory cells for storing data are connected in series and a selection gate transistor being provided at one end of the memory string, the selection wire connecting to each of the memory cells, and the gate wire connecting to the selection gate transistor; and

a drive circuit applying voltages to the selection wire and the gate wire during erase verification operation for confirming erasing of data in the memory cells,

the memory cell adjacent to the selection gate transistor being defined as a first memory cell, the memory cell adjacent to the first memory cell being defined as a second memory cell, the memory cell adjacent to the first memory cell being defined as a second memory cell, a voltage applied to the gate wire being defined as a gate wire voltage, a voltage applied to the selection wire connected to the first memory cell being defined as a first selection wire voltage, and a voltage applied to the selection wire connected to the second memory cell being defined as a second selection wire voltage, and

when the second selection wire voltage is lower than the gate wire voltage in the erase verification operation, the drive circuit controlling the voltages so that a difference between the gate wire voltage and the second selection wire voltage is less than a difference between the gate wire voltage and the first selection wire voltage.

15. The nonvolatile semiconductor storage device according to claim 14, wherein the memory cells of the memory string that are connected to odd-numbered points or even-numbered points are adopted as targets of the erase verification operation.

16. The nonvolatile semiconductor storage device according to claim 14, wherein

a memory cell of the memory string connected at one of an odd-numbered point and an even-numbered point is defined as a first target cell, and a memory cell of the memory string connected at the other of the odd-numbered point and the even-numbered point is defined as a second target cell, and

the drive circuit repeatedly executes the erase operation for erasing the data in the memory cells and the erase verification operation for the first target cell until the erase verification operation is passed, and thereafter repeatedly executes the erase verification operation for the second target cell along with the erase operation until the erase verification operation is passed.

17. The nonvolatile semiconductor storage device according to claim 14, wherein

the memory string includes the first memory cell, the second memory cell, and a third memory cell is the other memory cell,

a voltage applied to the selection wire connected to the third memory cell is defined as a third selection wire voltage, and

the drive circuit makes the third selection wire voltage the same as the second wire selection voltage in the erase verification operation.