Flash memory with bias voltage for word line/row driver
First Claim
Patent Images
1. A memory comprising:
- a word line driver circuit;
a write voltage generator for providing a write voltage to the word line driver during a write operation to memory cells coupled to the word line driver circuit;
a write bias generator including an output node for providing a write bias voltage that is different from the write voltage to the word line driver circuit during a write operation to memory cells coupled to the word line driver circuit, wherein the write bias voltage is used to reduce current drawn by the word line driver circuit from the write voltage generator during a write operation to memory cells coupled to the word line driver circuit, wherein the write bias generator includes;
a diode configured transistor including a first current terminal for receiving the write voltage and a second current terminal connected to the output node;
a first transistor having a first current terminal connected to the output node, a second current terminal, and a control terminal;
a second transistor having a first current terminal for receiving the write voltage, a second current terminal connected to the control terminal of the first transistor, and a control terminal connected to the output node, wherein during a write mode, the conductivity of the second transistor controls the conductivity of the first transistor for regulating the voltage of the output node.
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Abstract
A memory device includes a word line driver circuit, a write voltage generator for providing a write voltage to the word line driver during a write operation to memory cells coupled to the word line driver circuit, and a write bias generator including an output node for providing a write bias voltage that is different from the write voltage to the word line driver circuit during a write operation to memory cells coupled to the word line driver circuit. The write bias voltage is used to reduce current drawn by the word line driver circuit from the write voltage generator during a write operation to memory cells coupled to the word line driver circuit.
103 Citations
21 Claims
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1. A memory comprising:
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a word line driver circuit; a write voltage generator for providing a write voltage to the word line driver during a write operation to memory cells coupled to the word line driver circuit; a write bias generator including an output node for providing a write bias voltage that is different from the write voltage to the word line driver circuit during a write operation to memory cells coupled to the word line driver circuit, wherein the write bias voltage is used to reduce current drawn by the word line driver circuit from the write voltage generator during a write operation to memory cells coupled to the word line driver circuit, wherein the write bias generator includes; a diode configured transistor including a first current terminal for receiving the write voltage and a second current terminal connected to the output node; a first transistor having a first current terminal connected to the output node, a second current terminal, and a control terminal; a second transistor having a first current terminal for receiving the write voltage, a second current terminal connected to the control terminal of the first transistor, and a control terminal connected to the output node, wherein during a write mode, the conductivity of the second transistor controls the conductivity of the first transistor for regulating the voltage of the output node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of operating a word line driver comprising:
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performing a write operation to memory cells coupled to a word line driver, the performing a write operation includes; providing a write voltage to the word line driver from an output of a write voltage generator; providing a write bias voltage to the word line driver from an output of a write bias generator, wherein the word line driver uses the write bias voltage to reduce current drawn by the word line driver circuit from the write voltage generator output during the write operation to the memory cells coupled to the word line driver circuit, wherein the providing the write bias voltage includes the write bias generator receiving the write voltage from the output of the write voltage generator and using a first transistor and second transistor in generating the write bias voltage from the write voltage; operating in a read recovery mode following the write operation, the operating in a read recovery mode includes; receiving, by the write bias generator, a voltage from the output of the write voltage generator; using, by the write bias generator, the voltage provided by the output of the write voltage generator to generate a bias voltage at the output of the write bias generator without the use of the first transistor and the second transistor. - View Dependent Claims (20, 21)
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Specification