Increasing throughput of multiplexed electrical bus in pipe-lined architecture
First Claim
1. A method for increasing a throughput of an electrical bus that connects at least two devices in a system, comprising:
- introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices;
wherein each of the two devices comprises a pipelined architecture with one or more pipeline stages for buffering signals, and the signal-transmitting one of the two devices comprises a multiplexer for multiplexing buffered signals from at least one pipeline stage to generate a multiplexed signal that is propagated over the electrical bus, and the signal-receiving one of the two devices comprises a de-multiplexer for de-multiplexing the multiplexed signal received over the electrical bus.
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Accused Products
Abstract
Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.
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Citations
15 Claims
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1. A method for increasing a throughput of an electrical bus that connects at least two devices in a system, comprising:
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introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices; wherein each of the two devices comprises a pipelined architecture with one or more pipeline stages for buffering signals, and the signal-transmitting one of the two devices comprises a multiplexer for multiplexing buffered signals from at least one pipeline stage to generate a multiplexed signal that is propagated over the electrical bus, and the signal-receiving one of the two devices comprises a de-multiplexer for de-multiplexing the multiplexed signal received over the electrical bus. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for increasing a throughput of an electrical bus that connects at least two devices in a system, wherein an operating frequency of the two devices is a function of an operating frequency of the electrical bus divided by a total latency value, and wherein each of the two devices comprises a pipelined architecture with one or more pipeline stages for buffering signals, and the signal-transmitting one of the two devices comprises a multiplexer for multiplexing buffered signals from at least one pipeline stage to generate a multiplexed signal that is propagated over the electrical bus, and the signal-receiving one of the two devices comprises a de-multiplexer for de-multiplexing the multiplexed signal received over the electrical bus, the method comprising:
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removing at least one pipeline stage from the signal-transmitting one of the two devices; and adding at least one signal hold stage in a signal-receiving one of the two devices, such that the operating frequency of the two devices is increased, the total latency value is decreased, and a cycle-accuracy is maintained between the two devices with respect to state prior to the removal and addition steps and a state after the removal and addition steps. - View Dependent Claims (9, 10, 11, 12, 14, 15)
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13. A method for increasing a throughput of an electrical bus that connects at least two devices in a system, wherein an operating frequency of the two devices is a function of an operating frequency of the electrical bus divided by a total latency value, and wherein each of the two devices comprises a pipelined architecture with one or more pipeline stages for buffering signals, and the signal-transmitting one of the two devices comprises a multiplexer for multiplexing buffered signals from at least one pipeline stage to generate a multiplexed signal that is propagated over the electrical bus, and the signal-receiving one of the two devices comprises a de-multiplexer for de-multiplexing the multiplexed signal received over the electrical bus, the method comprising:
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removing at least one pipeline stage from the signal-transmitting one of the two devices; and adding at least one signal hold stage in a signal-receiving one of the two devices, such that the operating frequency of the two devices is increased, the total latency value is decreased, and a cycle-accuracy is maintained between the two devices with respect to state prior to the removal and addition steps and a state after the removal and addition steps; given that P is a number of signals to be routed from the signal-transmitting one of the two devices to the signal-receiving one of the two devices, C is a number of wires in the electrical bus, M is a multiplex ratio defined as M equals P divided by C, Ft is the operating frequency of the electrical bus, N is a number of cycles of the operating frequency Ft of the electrical bus needed for a signal to propagate from the signal-transmitting one of the two devices to the signal-receiving one of the two devices, B is a number of extra cycles of the operating frequency Ft of the electrical bus needed to compensate for clock phase differences between the signal-transmitting one of the two devices to the signal-receiving one of the two devices, and a maximum frequency Fs at which the two devices are operated is defined as Fs equals Ft divided by the sum of M, N and B, where M, N and B comprise the total latency value; the removal of the at least one pipeline stage from the signal-transmitting one of the two devices and the addition of the at least one signal hold stage in a signal-receiving one of the two device decreases the total latency value by masking latencies attributable to N and B thereby increasing the maximum operating frequency Fs of the two devices and thus the throughput of the electrical bus.
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Specification